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Commit f878cdd

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Fix non-critical Spyglass warnings
1 parent 55d777e commit f878cdd

2 files changed

Lines changed: 13 additions & 6 deletions

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src/snitch_icache_l0.sv

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -135,11 +135,18 @@ module snitch_icache_l0
135135
assign hit_prefetch_any = |hit_prefetch;
136136
assign miss = ~hit_any & in_valid_i & ~pending_refill_q & ~prefetching_missed_line;
137137

138+
// Only needed when EARLY_LATCH=1: clk_inv drives the clock gate in gen_latch.
139+
// Without the generate guard, i_clk_inv is removed as a hanging instance when
140+
// EARLY_LATCH=0 because clk_inv has no fanout in that configuration.
138141
logic clk_inv;
139-
tc_clk_inverter i_clk_inv (
140-
.clk_i(clk_i),
141-
.clk_o(clk_inv)
142-
);
142+
if (CFG.EARLY_LATCH) begin : gen_clk_inv
143+
tc_clk_inverter i_clk_inv (
144+
.clk_i(clk_i),
145+
.clk_o(clk_inv)
146+
);
147+
end else begin : gen_no_clk_inv
148+
assign clk_inv = '0;
149+
end
143150

144151
for (genvar i = 0; i < CFG.L0_LINE_COUNT; i++) begin : gen_array
145152
// Tag Array

src/snitch_icache_lookup_parallel.sv

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ module snitch_icache_lookup_parallel
8585
ram_enable = '0;
8686
ram_write = 1'b0;
8787

88-
if (init_count_q != $unsigned(CFG.LINE_COUNT)) begin
88+
if (init_count_q != CFG.LINE_COUNT) begin
8989
ram_addr = init_count_q;
9090
ram_enable = '1;
9191
ram_write = 1'b1;
@@ -107,7 +107,7 @@ module snitch_icache_lookup_parallel
107107

108108
always_ff @(posedge clk_i, negedge rst_ni) begin
109109
if (!rst_ni) init_count_q <= '0;
110-
else if (init_count_q != $unsigned(CFG.LINE_COUNT)) init_count_q <= init_count_q + 1;
110+
else if (init_count_q != CFG.LINE_COUNT) init_count_q <= init_count_q + 1;
111111
else if (flush_valid_i) init_count_q <= '0;
112112
end
113113

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