From d5d9c56b2c0fc310273a5495cf6db2b75517220c Mon Sep 17 00:00:00 2001 From: Luca Colagrande Date: Wed, 6 May 2026 15:15:10 +0200 Subject: [PATCH 1/4] l0: Cleanup after removal of non-resettable FFs --- src/snitch_icache_l0.sv | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/src/snitch_icache_l0.sv b/src/snitch_icache_l0.sv index 4ab6507..46e84de 100644 --- a/src/snitch_icache_l0.sv +++ b/src/snitch_icache_l0.sv @@ -71,11 +71,7 @@ module snitch_icache_l0 logic latch_prefetch, last_cycle_was_prefetch_q; prefetch_req_t prefetcher_out; - // As we have different flipflops (resetable vs non-resetable) we need to - // split that struct into two distinct signals to avoid multi-driven warnings - // in Verilator. - logic prefetch_req_vld_q, prefetch_req_vld_d; - logic [CFG.FETCH_AW-1:0] prefetch_req_addr_q, prefetch_req_addr_d; + prefetch_req_t prefetch_req_q, prefetch_req_d; // Holds the onehot signal for the line being refilled at the moment logic [CFG.L0_LINE_COUNT-1:0] pending_line_refill_q; @@ -425,27 +421,25 @@ module snitch_icache_l0 // check whether cache-line we want to pre-fetch is already present assign addr_tag_prefetch = CFG.L0_TAG_WIDTH'(prefetcher_out.addr >> CFG.LINE_ALIGN); - assign latch_prefetch = prefetcher_out.vld & ~prefetch_req_vld_q; + assign latch_prefetch = prefetcher_out.vld & ~prefetch_req_q.vld; always_comb begin - prefetch_req_vld_d = prefetch_req_vld_q; - prefetch_req_addr_d = prefetch_req_addr_q; + prefetch_req_d = prefetch_req_q; - if (prefetch_ready) prefetch_req_vld_d = 1'b0; + if (prefetch_ready) prefetch_req_d.vld = 1'b0; if (latch_prefetch) begin - prefetch_req_vld_d = 1'b1; - prefetch_req_addr_d = prefetcher_out.addr; + prefetch_req_d.vld = 1'b1; + prefetch_req_d.addr = prefetcher_out.addr; end end - assign addr_tag_prefetch_req = CFG.L0_TAG_WIDTH'(prefetch_req_addr_q >> CFG.LINE_ALIGN); + assign addr_tag_prefetch_req = CFG.L0_TAG_WIDTH'(prefetch_req_q.addr >> CFG.LINE_ALIGN); assign prefetch.is_prefetch = 1'b1; - assign prefetch.addr = prefetch_req_addr_q; - assign prefetch_valid = prefetch_req_vld_q; + assign prefetch.addr = prefetch_req_q.addr; + assign prefetch_valid = prefetch_req_q.vld; - `FF(prefetch_req_vld_q, prefetch_req_vld_d, '0) - `FF(prefetch_req_addr_q, prefetch_req_addr_d, '0) + `FF(prefetch_req_q, prefetch_req_d, '0) // ------------------ // Performance Events From 12bf7d077ff1d1e4d450bd3afc0f12a927e21a20 Mon Sep 17 00:00:00 2001 From: Luca Colagrande Date: Wed, 6 May 2026 18:10:34 +0200 Subject: [PATCH 2/4] l0: Filter prefetching requests on invalid hit --- src/snitch_icache_l0.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/snitch_icache_l0.sv b/src/snitch_icache_l0.sv index 46e84de..8a7a41f 100644 --- a/src/snitch_icache_l0.sv +++ b/src/snitch_icache_l0.sv @@ -320,7 +320,7 @@ module snitch_icache_l0 // ------------- // Generate a prefetch request if the cache hits and we haven't // pre-fetched the line yet and there is no other refill in progress. - assign prefetcher_out.vld = enable_prefetching_i & + assign prefetcher_out.vld = enable_prefetching_i & in_valid_i & hit_any & ~hit_prefetch_any & hit_early_is_onehot & ~pending_prefetch_q; From 55d777ec559d5905f8a6b56d3710b239b7a93675 Mon Sep 17 00:00:00 2001 From: Luca Colagrande Date: Sat, 16 May 2026 15:19:51 +0200 Subject: [PATCH 3/4] Bump common_cells to v2 --- Bender.yml | 2 +- src/multi_accept_rr_arb.sv | 18 ++++----- src/snitch_axi_to_cache.sv | 34 ++++++++-------- src/snitch_icache.sv | 60 ++++++++++++++-------------- src/snitch_icache_handler.sv | 10 +++-- src/snitch_icache_l0.sv | 6 +-- src/snitch_icache_lookup_parallel.sv | 10 ++--- src/snitch_icache_lookup_serial.sv | 5 ++- src/snitch_icache_refill.sv | 55 +++++++++++++------------ src/snitch_read_only_cache.sv | 10 ++--- test/snitch_icache_l0_tb.sv | 4 +- 11 files changed, 108 insertions(+), 106 deletions(-) diff --git a/Bender.yml b/Bender.yml index a5876d1..9acbf86 100644 --- a/Bender.yml +++ b/Bender.yml @@ -12,7 +12,7 @@ package: - "Michael Rogenmoser " dependencies: - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.28.0 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: v2-dev } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 } axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 } scm: { git: "https://github.com/pulp-platform/scm.git", version: 1.1.0 } diff --git a/src/multi_accept_rr_arb.sv b/src/multi_accept_rr_arb.sv index cd6ca06..745b131 100644 --- a/src/multi_accept_rr_arb.sv +++ b/src/multi_accept_rr_arb.sv @@ -10,7 +10,7 @@ module multi_accept_rr_arb #( ) ( input logic clk_i, input logic rst_ni, - input logic flush_i, + input logic clr_i, input data_t [NumInp-1:0] inp_data_i, input logic [NumInp-1:0] inp_valid_i, @@ -32,7 +32,7 @@ module multi_accept_rr_arb #( if (!rst_ni) begin lock_q <= '0; end else begin - if (flush_i) begin + if (clr_i) begin lock_q <= '0; end else begin lock_q <= lock_d; @@ -44,7 +44,7 @@ module multi_accept_rr_arb #( if (!rst_ni) begin req_q <= '0; end else begin - if (flush_i) begin + if (clr_i) begin req_q <= '0; end else begin req_q <= req_d; @@ -59,8 +59,8 @@ module multi_accept_rr_arb #( `ifndef COMMON_CELLS_ASSERTS_OFF lock : assert property( - @(posedge clk_i) disable iff (!rst_ni || flush_i) - oup_valid_o && (!oup_ready_i && !flush_i) |=> idx == $past( + @(posedge clk_i) disable iff (!rst_ni || clr_i) + oup_valid_o && (!oup_ready_i && !clr_i) |=> idx == $past( idx )) else $fatal(1, "Lock implies same arbiter decision in next cycle if output is not ready."); @@ -70,7 +70,7 @@ module multi_accept_rr_arb #( // over `posedge clk_i`. lock_req : assume property( - @(posedge clk_i) disable iff (!rst_ni || flush_i) + @(posedge clk_i) disable iff (!rst_ni || clr_i) lock_q |-> inp_valid_i[idx] == req_q[idx]) else $fatal(1, "It is disallowed to deassert the selected unserved request signals."); `endif @@ -79,16 +79,16 @@ module multi_accept_rr_arb #( - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (NumInp), - .DataType (data_t), + .data_t (data_t), .ExtPrio (1'b0), .AxiVldRdy(1'b1), .LockIn (1'b0) ) i_arbiter ( .clk_i, .rst_ni, - .flush_i, + .clr_i, .rr_i ('0), .req_i (req_d), .gnt_o (inp_ready_o), diff --git a/src/snitch_axi_to_cache.sv b/src/snitch_axi_to_cache.sv index b45cde3..0b736cc 100644 --- a/src/snitch_axi_to_cache.sv +++ b/src/snitch_axi_to_cache.sv @@ -39,7 +39,7 @@ module snitch_axi_to_cache #( output resp_t slv_rsp_o ); - import cf_math_pkg::idx_width; + import cc_pkg::idx_width; // AXI-word offset within cache line localparam int unsigned WordOffset = idx_width(CFG.LINE_WIDTH / CFG.FETCH_DW); @@ -207,8 +207,8 @@ module snitch_axi_to_cache #( assign rsp_in_d.error = rsp_error_i; assign rsp_in_d.id = rsp_id_i; - spill_register #( - .T (rsp_in_t), + cc_spill_register #( + .data_t(rsp_in_t), .Bypass(1'b0) ) i_cut_rsp_in ( .clk_i (clk_i), @@ -235,9 +235,9 @@ module snitch_axi_to_cache #( assign rsp_valid = rsp_valid_q; // And not empty? assign rsp_id_masked = rsp_in_q.id & ~rsp_id_mask; - lzc #( - .WIDTH(CFG.ID_WIDTH), - .MODE (0) + cc_lzc #( + .Width(CFG.ID_WIDTH), + .Mode (0) ) i_lzc ( .in_i (rsp_id_masked), .cnt_o (rsp_id), @@ -395,8 +395,8 @@ module axi_burst_splitter_table #( offset_t cnt_offset_inp; offset_t [MaxTrans-1:0] cnt_offset_oup; for (genvar i = 0; i < MaxTrans; i++) begin : gen_cnt - counter #( - .WIDTH($bits(cnt_t)) + cc_counter #( + .Width($bits(cnt_t)) ) i_cnt_len ( .clk_i, .rst_ni, @@ -408,8 +408,8 @@ module axi_burst_splitter_table #( .q_o (cnt_len_oup[i]), .overflow_o() // not used ); - counter #( - .WIDTH($bits(offset_t)) + cc_counter #( + .Width($bits(offset_t)) ) i_cnt_offset ( .clk_i, .rst_ni, @@ -426,9 +426,9 @@ module axi_burst_splitter_table #( assign cnt_len_inp = {1'b0, alloc_len_i} + 1; assign cnt_offset_inp = alloc_offset_i; - lzc #( - .WIDTH(MaxTrans), - .MODE (1'b0) + cc_lzc #( + .Width(MaxTrans), + .Mode (1'b0) ) i_lzc ( .in_i (cnt_free), .cnt_o (cnt_free_idx), @@ -437,10 +437,10 @@ module axi_burst_splitter_table #( logic idq_inp_req, idq_inp_gnt; logic idq_oup_gnt, idq_oup_valid, idq_oup_pop; - id_queue #( - .ID_WIDTH($bits(id_t)), - .CAPACITY(MaxTrans), - .FULL_BW (1'b1), + cc_id_queue #( + .IdWidth ($bits(id_t)), + .Capacity(MaxTrans), + .FullBw (1'b1), .data_t (cnt_idx_t) ) i_idq ( .clk_i, diff --git a/src/snitch_icache.sv b/src/snitch_icache.sv index c38d82c..5f00889 100644 --- a/src/snitch_icache.sv +++ b/src/snitch_icache.sv @@ -280,8 +280,8 @@ module snitch_icache .out_rsp_ready_o(local_prefetch_rsp_ready) ); - isochronous_spill_register #( - .T (prefetch_req_t), + cc_isochronous_spill_register #( + .data_t(prefetch_req_t), .Bypass(!ISO_CROSSING) ) i_spill_register_prefetch_req ( .src_clk_i (clk_d2_i), @@ -296,8 +296,8 @@ module snitch_icache .dst_data_o (prefetch_req[i]) ); - isochronous_spill_register #( - .T (prefetch_resp_t), + cc_isochronous_spill_register #( + .data_t(prefetch_resp_t), .Bypass(!ISO_CROSSING) ) i_spill_register_prefetch_resp ( .src_clk_i (clk_i), @@ -339,8 +339,8 @@ module snitch_icache assign bypass_req.id = '0; - isochronous_spill_register #( - .T (miss_refill_req_t), + cc_isochronous_spill_register #( + .data_t(miss_refill_req_t), .Bypass(!ISO_CROSSING) ) i_spill_register_bypass_req ( .src_clk_i (clk_d2_i), @@ -355,8 +355,8 @@ module snitch_icache .dst_data_o (bypass_req_q) ); - isochronous_spill_register #( - .T (miss_refill_rsp_t), + cc_isochronous_spill_register #( + .data_t(miss_refill_rsp_t), .Bypass(!ISO_CROSSING) ) i_spill_register_bypass_resp ( .src_clk_i (clk_i), @@ -421,7 +421,7 @@ module snitch_icache ) i_stream_arbiter_pre ( .clk_i, .rst_ni, - .flush_i ('0), + .clr_i ('0), .inp_data_i (prefetch_req), .inp_valid_i(prefetch_req_valid & ~prefetch_req_priority), .inp_ready_o(prefetch_req_ready_pre), @@ -437,7 +437,7 @@ module snitch_icache ) i_stream_arbiter_fetch ( .clk_i, .rst_ni, - .flush_i ('0), + .clr_i ('0), .inp_data_i (prefetch_req), .inp_valid_i(prefetch_req_valid & prefetch_req_priority), .inp_ready_o(prefetch_req_ready_fetch), @@ -456,7 +456,7 @@ module snitch_icache ) i_stream_arbiter ( .clk_i, .rst_ni, - .flush_i ('0), + .clr_i ('0), .inp_data_i (prefetch_req), .inp_valid_i(prefetch_req_valid), .inp_ready_o(prefetch_req_ready_tmp), @@ -673,12 +673,13 @@ module snitch_icache ); assign handler_req.bypass = 1'b0; // Arbitrate between bypass and cache-refills - stream_arbiter #( - .DATA_T(miss_refill_req_t), - .N_INP (2) + cc_stream_arbiter #( + .data_t(miss_refill_req_t), + .NumInp(2) ) i_stream_arbiter_miss_refill ( .clk_i, .rst_ni, + .clr_i (1'b0), .inp_data_i ({bypass_req_q, handler_req}), .inp_valid_i({bypass_req_valid_q, handler_req_valid}), .inp_ready_o({bypass_req_ready_q, handler_req_ready}), @@ -687,8 +688,8 @@ module snitch_icache .oup_ready_i(refill_req_ready) ); // Response path muxing - stream_demux #( - .N_OUP(2) + cc_stream_demux #( + .NumOup(2) ) i_stream_demux_miss_refill ( .inp_valid_i(refill_rsp_valid), .inp_ready_o(refill_rsp_ready), @@ -774,12 +775,13 @@ module l0_to_bypass #( in_addr_i[i][CFG.FETCH_AW-1:CFG.LINE_ALIGN], {CFG.LINE_ALIGN{1'b0}} }; end - stream_arbiter #( - .DATA_T(logic [CFG.FETCH_AW-1:0]), - .N_INP (CFG.NR_FETCH_PORTS) + cc_stream_arbiter #( + .data_t(logic [CFG.FETCH_AW-1:0]), + .NumInp(CFG.NR_FETCH_PORTS) ) i_stream_arbiter ( .clk_i, .rst_ni, + .clr_i (1'b0), .inp_data_i (in_addr_masked), .inp_valid_i(in_valid), .inp_ready_o(in_ready), @@ -800,14 +802,14 @@ module l0_to_bypass #( logic [CFG.NR_FETCH_PORTS-1:0] rsp_valid; logic [CFG.NR_FETCH_PORTS-1:0] rsp_ready; - fifo_v3 #( - .DATA_WIDTH(CFG.NR_FETCH_PORTS), - .DEPTH (4) + cc_fifo #( + .DataWidth(CFG.NR_FETCH_PORTS), + .Depth (4) ) rsp_fifo ( .clk_i, .rst_ni, + .clr_i (1'b0), .flush_i (1'b0), - .testmode_i(1'b0), .full_o (rsp_fifo_full), .empty_o (), .usage_o (), @@ -818,17 +820,17 @@ module l0_to_bypass #( ); - onehot_to_bin #( - .ONEHOT_WIDTH(CFG.NR_FETCH_PORTS) + cc_onehot_to_bin #( + .OnehotWidth(CFG.NR_FETCH_PORTS) ) i_onehot_to_bin ( - .onehot(rsp_fifo_mux), - .bin (onehot_mux) + .onehot_i(rsp_fifo_mux), + .bin_o (onehot_mux) ); assign rsp_ready = '1; - stream_demux #( - .N_OUP(CFG.NR_FETCH_PORTS) + cc_stream_demux #( + .NumOup(CFG.NR_FETCH_PORTS) ) i_stream_mux_miss_refill ( .inp_valid_i(refill_rsp_valid_i), .inp_ready_o(refill_rsp_ready_o), diff --git a/src/snitch_icache_handler.sv b/src/snitch_icache_handler.sv index 9b34f2a..e8a8bfb 100644 --- a/src/snitch_icache_handler.sv +++ b/src/snitch_icache_handler.sv @@ -132,8 +132,9 @@ module snitch_icache_handler free = |free_entries; end - lzc #( - .WIDTH(CFG.PENDING_COUNT) + cc_lzc #( + .Width(CFG.PENDING_COUNT), + .Mode (cc_pkg::LZC_TRAILING_ZERO_CNT) ) i_lzc_free ( .in_i (free_entries), .cnt_o (free_id), @@ -152,8 +153,9 @@ module snitch_icache_handler pending = |pending_matches; end - lzc #( - .WIDTH(CFG.PENDING_COUNT) + cc_lzc #( + .Width(CFG.PENDING_COUNT), + .Mode (cc_pkg::LZC_TRAILING_ZERO_CNT) ) i_lzc_pending ( .in_i (pending_matches), .cnt_o (pending_id), diff --git a/src/snitch_icache_l0.sv b/src/snitch_icache_l0.sv index 8a7a41f..46dc7e3 100644 --- a/src/snitch_icache_l0.sv +++ b/src/snitch_icache_l0.sv @@ -367,9 +367,9 @@ module snitch_icache_l0 logic [$clog2(CFG.LINE_WIDTH)-1:0] ins_idx; assign ins_idx = 32 * taken_idx; // Find first taken branch - lzc #( - .WIDTH(FetchPkts), - .MODE (0) + cc_lzc #( + .Width(FetchPkts), + .Mode (cc_pkg::LZC_TRAILING_ZERO_CNT) ) i_lzc_branch ( // look at branches and jals .in_i (mask & (is_branch_taken | is_jal)), diff --git a/src/snitch_icache_lookup_parallel.sv b/src/snitch_icache_lookup_parallel.sv index 6e47ca8..7ce91af 100644 --- a/src/snitch_icache_lookup_parallel.sv +++ b/src/snitch_icache_lookup_parallel.sv @@ -254,8 +254,9 @@ module snitch_icache_lookup_parallel end end - lzc #( - .WIDTH(CFG.WAY_COUNT) + cc_lzc #( + .Width(CFG.WAY_COUNT), + .Mode (cc_pkg::LZC_TRAILING_ZERO_CNT) ) i_lzc ( .in_i (line_hit), .cnt_o (data_d.cway), @@ -264,13 +265,12 @@ module snitch_icache_lookup_parallel // Buffer response in case we are stalled if (CFG.BUFFER_LOOKUP) begin : gen_buffer - fall_through_register #( - .T(out_buffer_t) + cc_fall_through_register #( + .data_t(out_buffer_t) ) i_rsp_buffer ( .clk_i (clk_i), .rst_ni (rst_ni), .clr_i (1'b0), - .testmode_i(1'b0), // Input port .valid_i (valid_q), .ready_o (buffer_ready), diff --git a/src/snitch_icache_lookup_serial.sv b/src/snitch_icache_lookup_serial.sv index 22748c8..ecd069d 100644 --- a/src/snitch_icache_lookup_serial.sv +++ b/src/snitch_icache_lookup_serial.sv @@ -203,8 +203,9 @@ module snitch_icache_lookup_serial assign tag_rsp_s.hit = |line_hit; assign tag_rsp_s.error = |errors; - lzc #( - .WIDTH(CFG.WAY_COUNT) + cc_lzc #( + .Width(CFG.WAY_COUNT), + .Mode (cc_pkg::LZC_TRAILING_ZERO_CNT) ) i_lzc ( .in_i (line_hit), .cnt_o (tag_rsp_s.cway), diff --git a/src/snitch_icache_refill.sv b/src/snitch_icache_refill.sv index 1a4d199..60671e4 100644 --- a/src/snitch_icache_refill.sv +++ b/src/snitch_icache_refill.sv @@ -45,21 +45,21 @@ module snitch_icache_refill #( localparam int unsigned TransactionQueueDepth = 4; - fifo_v3 #( - .DEPTH (TransactionQueueDepth), - .DATA_WIDTH(CFG.PENDING_IW + 1) + cc_fifo #( + .Depth (TransactionQueueDepth), + .DataWidth(CFG.PENDING_IW + 1) ) i_fifo_id_queue ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .flush_i (1'b0), - .testmode_i(1'b0), - .full_o (queue_full), - .empty_o (), - .usage_o (), - .data_i ({in_req_bypass_i, in_req_id_i}), - .push_i (queue_push), - .data_o ({in_rsp_bypass_o, in_rsp_id_o}), - .pop_i (queue_pop) + .clk_i (clk_i), + .rst_ni (rst_ni), + .clr_i (1'b0), + .flush_i(1'b0), + .full_o (queue_full), + .empty_o(), + .usage_o(), + .data_i ({in_req_bypass_i, in_req_id_i}), + .push_i (queue_push), + .data_o ({in_rsp_bypass_o, in_rsp_id_o}), + .pop_i (queue_pop) ); // Accept incoming requests, push the ID into the queue, and issue the @@ -83,21 +83,20 @@ module snitch_icache_refill #( end else if (CFG.LINE_WIDTH < CFG.FILL_DW) begin : g_data_slice localparam int unsigned AddrQueueDepth = CFG.FILL_ALIGN - CFG.LINE_ALIGN; logic [AddrQueueDepth-1:0] addr_offset; - fifo_v3 #( - .DEPTH (TransactionQueueDepth), - .DATA_WIDTH(AddrQueueDepth) + cc_fifo #( + .Depth (TransactionQueueDepth), + .DataWidth(AddrQueueDepth) ) i_fifo_addr_offset ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .flush_i (1'b0), - .testmode_i(1'b0), - .full_o ( /* same size as the `i_fifo_id_queue` */), - .empty_o (), - .usage_o (), - .data_i (in_req_addr_i[CFG.FILL_ALIGN-1:CFG.LINE_ALIGN]), - .push_i (queue_push), - .data_o (addr_offset), - .pop_i (queue_pop) + .clk_i (clk_i), + .rst_ni (rst_ni), + .clr_i (1'b0), + .full_o ( /* same size as the `i_fifo_id_queue` */), + .empty_o(), + .usage_o(), + .data_i (in_req_addr_i[CFG.FILL_ALIGN-1:CFG.LINE_ALIGN]), + .push_i (queue_push), + .data_o (addr_offset), + .pop_i (queue_pop) ); assign response_data = axi_rsp_i.r.data >> (addr_offset * CFG.LINE_WIDTH); end else begin : g_data_passthrough diff --git a/src/snitch_read_only_cache.sv b/src/snitch_read_only_cache.sv index 8428719..eb18c69 100644 --- a/src/snitch_read_only_cache.sv +++ b/src/snitch_read_only_cache.sv @@ -60,7 +60,7 @@ module snitch_read_only_cache `include "axi/typedef.svh" `include "common_cells/registers.svh" - import cf_math_pkg::idx_width; + import cc_pkg::idx_width; // Check for supported parameters if (AxiDataWidth < 32) $error("snitch_read_only_cache: AxiDataWidth must be larger than 32."); @@ -122,7 +122,6 @@ module snitch_read_only_cache ) i_axi_demux ( .clk_i, .rst_ni, - .test_i (1'b0), .slv_req_i (axi_slv_req_i), .slv_aw_select_i(slv_aw_select), .slv_ar_select_i(slv_ar_select), @@ -143,7 +142,7 @@ module snitch_read_only_cache assign addr_map[i] = '{idx: Cache, start_addr: start_addr_i[i], end_addr: end_addr_i[i]}; end - addr_decode #( + cc_addr_decode #( .NoIndices(NoMstPorts), .NoRules (NrAddrRules), .addr_t (addr_t), @@ -211,8 +210,8 @@ module snitch_read_only_cache FETCH_ALIGN: $clog2(AxiDataWidth / 8), FILL_ALIGN: $clog2(AxiDataWidth / 8), LINE_ALIGN: $clog2(LineWidth / 8), - COUNT_ALIGN: cf_math_pkg::idx_width(LineCount), - WAY_ALIGN: cf_math_pkg::idx_width(WayCount), + COUNT_ALIGN: cc_pkg::idx_width(LineCount), + WAY_ALIGN: cc_pkg::idx_width(WayCount), TAG_WIDTH: AxiAddrWidth - $clog2(LineWidth / 8) - $clog2(LineCount) + 1, ID_WIDTH: 2 ** AxiIdWidth, PENDING_IW: $clog2(PendingCount), @@ -469,7 +468,6 @@ module snitch_read_only_cache ) i_axi_mux ( .clk_i, .rst_ni, - .test_i (1'b0), .slv_reqs_i ({refill_req, demux_req[Bypass]}), .slv_resps_o({refill_rsp, demux_rsp[Bypass]}), .mst_req_o (axi_mst_req_o), diff --git a/test/snitch_icache_l0_tb.sv b/test/snitch_icache_l0_tb.sv index 1ec6839..80b5be9 100644 --- a/test/snitch_icache_l0_tb.sv +++ b/test/snitch_icache_l0_tb.sv @@ -126,13 +126,13 @@ module snitch_icache_l0_tb #( logic [IdWidth-1:0] id; } dut_out_t; - typedef stream_test::stream_driver#( + typedef cc_test_pkg::cc_stream_driver#( .payload_t(dut_in_t), .TA (TA), .TT (TT) ) stream_driver_in_t; - typedef stream_test::stream_driver#( + typedef cc_test_pkg::cc_stream_driver#( .payload_t(dut_out_t), .TA (TA), .TT (TT) From f878cdd1a48c4a2fcc9d6dcad5c8de41c10e1ebd Mon Sep 17 00:00:00 2001 From: Luca Colagrande Date: Tue, 2 Jun 2026 19:08:43 +0200 Subject: [PATCH 4/4] Fix non-critical Spyglass warnings --- src/snitch_icache_l0.sv | 15 +++++++++++---- src/snitch_icache_lookup_parallel.sv | 4 ++-- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/src/snitch_icache_l0.sv b/src/snitch_icache_l0.sv index 46dc7e3..5947259 100644 --- a/src/snitch_icache_l0.sv +++ b/src/snitch_icache_l0.sv @@ -135,11 +135,18 @@ module snitch_icache_l0 assign hit_prefetch_any = |hit_prefetch; assign miss = ~hit_any & in_valid_i & ~pending_refill_q & ~prefetching_missed_line; + // Only needed when EARLY_LATCH=1: clk_inv drives the clock gate in gen_latch. + // Without the generate guard, i_clk_inv is removed as a hanging instance when + // EARLY_LATCH=0 because clk_inv has no fanout in that configuration. logic clk_inv; - tc_clk_inverter i_clk_inv ( - .clk_i(clk_i), - .clk_o(clk_inv) - ); + if (CFG.EARLY_LATCH) begin : gen_clk_inv + tc_clk_inverter i_clk_inv ( + .clk_i(clk_i), + .clk_o(clk_inv) + ); + end else begin : gen_no_clk_inv + assign clk_inv = '0; + end for (genvar i = 0; i < CFG.L0_LINE_COUNT; i++) begin : gen_array // Tag Array diff --git a/src/snitch_icache_lookup_parallel.sv b/src/snitch_icache_lookup_parallel.sv index 7ce91af..80e10f4 100644 --- a/src/snitch_icache_lookup_parallel.sv +++ b/src/snitch_icache_lookup_parallel.sv @@ -85,7 +85,7 @@ module snitch_icache_lookup_parallel ram_enable = '0; ram_write = 1'b0; - if (init_count_q != $unsigned(CFG.LINE_COUNT)) begin + if (init_count_q != CFG.LINE_COUNT) begin ram_addr = init_count_q; ram_enable = '1; ram_write = 1'b1; @@ -107,7 +107,7 @@ module snitch_icache_lookup_parallel always_ff @(posedge clk_i, negedge rst_ni) begin if (!rst_ni) init_count_q <= '0; - else if (init_count_q != $unsigned(CFG.LINE_COUNT)) init_count_q <= init_count_q + 1; + else if (init_count_q != CFG.LINE_COUNT) init_count_q <= init_count_q + 1; else if (flush_valid_i) init_count_q <= '0; end