Bump common_cells to v2

Bender.yml

@@ -12,7 +12,7 @@ package:
     - "Michael Rogenmoser <michaero@iis.ee.ethz.ch>"
 
 dependencies:
-  common_cells:       { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.28.0 }
+  common_cells:       { git: "https://github.com/pulp-platform/common_cells.git",       rev: v2-dev }
   tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 }
   axi:                { git: "https://github.com/pulp-platform/axi.git",                version: 0.39.1 }
   scm:                { git: "https://github.com/pulp-platform/scm.git",                version: 1.1.0 }

src/multi_accept_rr_arb.sv

@@ -10,7 +10,7 @@ module multi_accept_rr_arb #(
 ) (
   input logic clk_i,
   input logic rst_ni,
-  input logic flush_i,
+  input logic clr_i,
 
   input  data_t [NumInp-1:0] inp_data_i,
   input  logic  [NumInp-1:0] inp_valid_i,
@@ -32,7 +32,7 @@ module multi_accept_rr_arb #(
     if (!rst_ni) begin
       lock_q <= '0;
     end else begin
-      if (flush_i) begin
+      if (clr_i) begin
         lock_q <= '0;
       end else begin
         lock_q <= lock_d;
@@ -44,7 +44,7 @@ module multi_accept_rr_arb #(
     if (!rst_ni) begin
       req_q <= '0;
     end else begin
-      if (flush_i) begin
+      if (clr_i) begin
         req_q <= '0;
       end else begin
         req_q <= req_d;
@@ -59,8 +59,8 @@ module multi_accept_rr_arb #(
 `ifndef COMMON_CELLS_ASSERTS_OFF
   lock :
   assert property(
-      @(posedge clk_i) disable iff (!rst_ni || flush_i)
-          oup_valid_o && (!oup_ready_i && !flush_i) |=> idx == $past(
+      @(posedge clk_i) disable iff (!rst_ni || clr_i)
+          oup_valid_o && (!oup_ready_i && !clr_i) |=> idx == $past(
       idx
   ))
   else $fatal(1, "Lock implies same arbiter decision in next cycle if output is not ready.");
@@ -70,7 +70,7 @@ module multi_accept_rr_arb #(
   // over `posedge clk_i`.
   lock_req :
   assume property(
-      @(posedge clk_i) disable iff (!rst_ni || flush_i)
+      @(posedge clk_i) disable iff (!rst_ni || clr_i)
           lock_q |-> inp_valid_i[idx] == req_q[idx])
   else $fatal(1, "It is disallowed to deassert the selected unserved request signals.");
 `endif
@@ -79,16 +79,16 @@ module multi_accept_rr_arb #(
 
 
 
-  rr_arb_tree #(
+  cc_rr_arb_tree #(
     .NumIn    (NumInp),
-    .DataType (data_t),
+    .data_t   (data_t),
     .ExtPrio  (1'b0),
     .AxiVldRdy(1'b1),
     .LockIn   (1'b0)
   ) i_arbiter (
     .clk_i,
     .rst_ni,
-    .flush_i,
+    .clr_i,
     .rr_i  ('0),
     .req_i (req_d),
     .gnt_o (inp_ready_o),

src/snitch_axi_to_cache.sv

@@ -39,7 +39,7 @@ module snitch_axi_to_cache #(
   output resp_t                      slv_rsp_o
 );
 
-  import cf_math_pkg::idx_width;
+  import cc_pkg::idx_width;
 
   // AXI-word offset within cache line
   localparam int unsigned WordOffset = idx_width(CFG.LINE_WIDTH / CFG.FETCH_DW);
@@ -207,8 +207,8 @@ module snitch_axi_to_cache #(
   assign rsp_in_d.error = rsp_error_i;
   assign rsp_in_d.id    = rsp_id_i;
 
-  spill_register #(
-    .T     (rsp_in_t),
+  cc_spill_register #(
+    .data_t(rsp_in_t),
     .Bypass(1'b0)
   ) i_cut_rsp_in (
     .clk_i  (clk_i),
@@ -235,9 +235,9 @@ module snitch_axi_to_cache #(
   assign rsp_valid     = rsp_valid_q;  // And not empty?
   assign rsp_id_masked = rsp_in_q.id & ~rsp_id_mask;
 
-  lzc #(
-    .WIDTH(CFG.ID_WIDTH),
-    .MODE (0)
+  cc_lzc #(
+    .Width(CFG.ID_WIDTH),
+    .Mode (0)
   ) i_lzc (
     .in_i   (rsp_id_masked),
     .cnt_o  (rsp_id),
@@ -395,8 +395,8 @@ module axi_burst_splitter_table #(
   offset_t                cnt_offset_inp;
   offset_t [MaxTrans-1:0] cnt_offset_oup;
   for (genvar i = 0; i < MaxTrans; i++) begin : gen_cnt
-    counter #(
-      .WIDTH($bits(cnt_t))
+    cc_counter #(
+      .Width($bits(cnt_t))
     ) i_cnt_len (
       .clk_i,
       .rst_ni,
@@ -408,8 +408,8 @@ module axi_burst_splitter_table #(
       .q_o       (cnt_len_oup[i]),
       .overflow_o()                 // not used
     );
-    counter #(
-      .WIDTH($bits(offset_t))
+    cc_counter #(
+      .Width($bits(offset_t))
     ) i_cnt_offset (
       .clk_i,
       .rst_ni,
@@ -426,9 +426,9 @@ module axi_burst_splitter_table #(
   assign cnt_len_inp    = {1'b0, alloc_len_i} + 1;
   assign cnt_offset_inp = alloc_offset_i;
 
-  lzc #(
-    .WIDTH(MaxTrans),
-    .MODE (1'b0)
+  cc_lzc #(
+    .Width(MaxTrans),
+    .Mode (1'b0)
   ) i_lzc (
     .in_i   (cnt_free),
     .cnt_o  (cnt_free_idx),
@@ -437,10 +437,10 @@ module axi_burst_splitter_table #(
 
   logic idq_inp_req, idq_inp_gnt;
   logic idq_oup_gnt, idq_oup_valid, idq_oup_pop;
-  id_queue #(
-    .ID_WIDTH($bits(id_t)),
-    .CAPACITY(MaxTrans),
-    .FULL_BW (1'b1),
+  cc_id_queue #(
+    .IdWidth ($bits(id_t)),
+    .Capacity(MaxTrans),
+    .FullBw  (1'b1),
     .data_t  (cnt_idx_t)
   ) i_idq (
     .clk_i,

src/snitch_icache.sv

@@ -280,8 +280,8 @@ module snitch_icache
       .out_rsp_ready_o(local_prefetch_rsp_ready)
     );
 
-    isochronous_spill_register #(
-      .T     (prefetch_req_t),
+    cc_isochronous_spill_register #(
+      .data_t(prefetch_req_t),
       .Bypass(!ISO_CROSSING)
     ) i_spill_register_prefetch_req (
       .src_clk_i  (clk_d2_i),
@@ -296,8 +296,8 @@ module snitch_icache
       .dst_data_o (prefetch_req[i])
     );
 
-    isochronous_spill_register #(
-      .T     (prefetch_resp_t),
+    cc_isochronous_spill_register #(
+      .data_t(prefetch_resp_t),
       .Bypass(!ISO_CROSSING)
     ) i_spill_register_prefetch_resp (
       .src_clk_i  (clk_i),
@@ -339,8 +339,8 @@ module snitch_icache
 
   assign bypass_req.id = '0;
 
-  isochronous_spill_register #(
-    .T     (miss_refill_req_t),
+  cc_isochronous_spill_register #(
+    .data_t(miss_refill_req_t),
     .Bypass(!ISO_CROSSING)
   ) i_spill_register_bypass_req (
     .src_clk_i  (clk_d2_i),
@@ -355,8 +355,8 @@ module snitch_icache
     .dst_data_o (bypass_req_q)
   );
 
-  isochronous_spill_register #(
-    .T     (miss_refill_rsp_t),
+  cc_isochronous_spill_register #(
+    .data_t(miss_refill_rsp_t),
     .Bypass(!ISO_CROSSING)
   ) i_spill_register_bypass_resp (
     .src_clk_i  (clk_i),
@@ -421,7 +421,7 @@ module snitch_icache
     ) i_stream_arbiter_pre (
       .clk_i,
       .rst_ni,
-      .flush_i    ('0),
+      .clr_i      ('0),
       .inp_data_i (prefetch_req),
       .inp_valid_i(prefetch_req_valid & ~prefetch_req_priority),
       .inp_ready_o(prefetch_req_ready_pre),
@@ -437,7 +437,7 @@ module snitch_icache
     ) i_stream_arbiter_fetch (
       .clk_i,
       .rst_ni,
-      .flush_i    ('0),
+      .clr_i      ('0),
       .inp_data_i (prefetch_req),
       .inp_valid_i(prefetch_req_valid & prefetch_req_priority),
       .inp_ready_o(prefetch_req_ready_fetch),
@@ -456,7 +456,7 @@ module snitch_icache
     ) i_stream_arbiter (
       .clk_i,
       .rst_ni,
-      .flush_i    ('0),
+      .clr_i      ('0),
       .inp_data_i (prefetch_req),
       .inp_valid_i(prefetch_req_valid),
       .inp_ready_o(prefetch_req_ready_tmp),
@@ -673,12 +673,13 @@ module snitch_icache
   );
   assign handler_req.bypass = 1'b0;
   // Arbitrate between bypass and cache-refills
-  stream_arbiter #(
-    .DATA_T(miss_refill_req_t),
-    .N_INP (2)
+  cc_stream_arbiter #(
+    .data_t(miss_refill_req_t),
+    .NumInp(2)
   ) i_stream_arbiter_miss_refill (
     .clk_i,
     .rst_ni,
+    .clr_i      (1'b0),
     .inp_data_i ({bypass_req_q, handler_req}),
     .inp_valid_i({bypass_req_valid_q, handler_req_valid}),
     .inp_ready_o({bypass_req_ready_q, handler_req_ready}),
@@ -687,8 +688,8 @@ module snitch_icache
     .oup_ready_i(refill_req_ready)
   );
   // Response path muxing
-  stream_demux #(
-    .N_OUP(2)
+  cc_stream_demux #(
+    .NumOup(2)
   ) i_stream_demux_miss_refill (
     .inp_valid_i(refill_rsp_valid),
     .inp_ready_o(refill_rsp_ready),
@@ -774,12 +775,13 @@ module l0_to_bypass #(
       in_addr_i[i][CFG.FETCH_AW-1:CFG.LINE_ALIGN], {CFG.LINE_ALIGN{1'b0}}
     };
   end
-  stream_arbiter #(
-    .DATA_T(logic [CFG.FETCH_AW-1:0]),
-    .N_INP (CFG.NR_FETCH_PORTS)
+  cc_stream_arbiter #(
+    .data_t(logic [CFG.FETCH_AW-1:0]),
+    .NumInp(CFG.NR_FETCH_PORTS)
   ) i_stream_arbiter (
     .clk_i,
     .rst_ni,
+    .clr_i      (1'b0),
     .inp_data_i (in_addr_masked),
     .inp_valid_i(in_valid),
     .inp_ready_o(in_ready),
@@ -800,14 +802,14 @@ module l0_to_bypass #(
   logic [CFG.NR_FETCH_PORTS-1:0] rsp_valid;
   logic [CFG.NR_FETCH_PORTS-1:0] rsp_ready;
 
-  fifo_v3 #(
-    .DATA_WIDTH(CFG.NR_FETCH_PORTS),
-    .DEPTH     (4)
+  cc_fifo #(
+    .DataWidth(CFG.NR_FETCH_PORTS),
+    .Depth     (4)
   ) rsp_fifo (
     .clk_i,
     .rst_ni,
+    .clr_i     (1'b0),
     .flush_i   (1'b0),
-    .testmode_i(1'b0),
     .full_o    (rsp_fifo_full),
     .empty_o   (),
     .usage_o   (),
@@ -818,17 +820,17 @@ module l0_to_bypass #(
   );
 
 
-  onehot_to_bin #(
-    .ONEHOT_WIDTH(CFG.NR_FETCH_PORTS)
+  cc_onehot_to_bin #(
+    .OnehotWidth(CFG.NR_FETCH_PORTS)
   ) i_onehot_to_bin (
-    .onehot(rsp_fifo_mux),
-    .bin   (onehot_mux)
+    .onehot_i(rsp_fifo_mux),
+    .bin_o   (onehot_mux)
   );
 
   assign rsp_ready = '1;
 
-  stream_demux #(
-    .N_OUP(CFG.NR_FETCH_PORTS)
+  cc_stream_demux #(
+    .NumOup(CFG.NR_FETCH_PORTS)
   ) i_stream_mux_miss_refill (
     .inp_valid_i(refill_rsp_valid_i),
     .inp_ready_o(refill_rsp_ready_o),

src/snitch_icache_handler.sv

@@ -132,8 +132,9 @@ module snitch_icache_handler
     free = |free_entries;
   end
 
-  lzc #(
-    .WIDTH(CFG.PENDING_COUNT)
+  cc_lzc #(
+    .Width(CFG.PENDING_COUNT),
+    .Mode (cc_pkg::LZC_TRAILING_ZERO_CNT)
   ) i_lzc_free (
     .in_i   (free_entries),
     .cnt_o  (free_id),
@@ -152,8 +153,9 @@ module snitch_icache_handler
     pending = |pending_matches;
   end
 
-  lzc #(
-    .WIDTH(CFG.PENDING_COUNT)
+  cc_lzc #(
+    .Width(CFG.PENDING_COUNT),
+    .Mode (cc_pkg::LZC_TRAILING_ZERO_CNT)
   ) i_lzc_pending (
     .in_i   (pending_matches),
     .cnt_o  (pending_id),