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klayout: generate seal rings without PCell registry
1 parent eda4c2e commit 3babeed

4 files changed

Lines changed: 98 additions & 2 deletions

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ihp13/.gitignore

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*.patched
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ihp-sg13g2

klayout/run_finishing.sh

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@@ -126,8 +126,7 @@ gen_seal_ring() {
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run_cmd "echo [INFO][KLayout] Read ../openroad/out/${PROJ_NAME}.def - die area: ${die_width} um x ${die_height} um"
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run_cmd "echo [INFO][KLayout] Chip dimensions with seal: ${seal_width} um x ${seal_height} um"
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run_cmd "klayout -nc -rx -zz \
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-rm $KLAYOUT_PATH/tech/pymacros/autorun.lym \
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-r $KLAYOUT_PATH/tech/scripts/sealring.py \
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-r scripts/generate_seal_ring.py \
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-rd width=$seal_width \
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-rd height=$seal_height \
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-rd output=out/seal_ring.gds.gz \
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"""Generate the IHP seal ring without KLayout's PCell registry."""
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import importlib.util
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import os
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import pathlib
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import re
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import sys
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import types
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import pya
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croc_root = os.environ["CROC_ROOT"]
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klayout_path = os.environ["KLAYOUT_PATH"]
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pdk = os.environ["CROC_PDK"]
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klayout_python = os.path.join(klayout_path, "python")
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shared_klayout_python = os.path.join(
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croc_root, "ihp13", "sg13g2", "ihp-sg13g2", "libs.tech", "klayout", "python"
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)
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sys.path.extend(
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[
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klayout_python,
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os.path.join(shared_klayout_python, "pycell4klayout-api", "source", "python"),
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]
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)
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from cni.dlo import PyCellContext
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from cni.tech import Tech
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if pdk == "sg13cmos5l":
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pcell_package = "sg13cmos5l_pycell_lib"
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elif pdk == "sg13g2":
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pcell_package = "sg13g2_pycell_lib"
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else:
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raise RuntimeError(f"Unsupported Croc PDK: {pdk}")
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package_name = f"croc_{pdk}_pcell"
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pcell_root = os.path.join(klayout_python, pcell_package)
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ihp_root = os.path.join(pcell_root, "ihp")
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package = types.ModuleType(package_name)
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package.__path__ = [pcell_root]
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sys.modules[package_name] = package
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ihp_package = types.ModuleType(f"{package_name}.ihp")
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ihp_package.__path__ = [ihp_root]
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sys.modules[ihp_package.__name__] = ihp_package
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def load_module(name, path):
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spec = importlib.util.spec_from_file_location(name, path)
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module = importlib.util.module_from_spec(spec)
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sys.modules[name] = module
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spec.loader.exec_module(module)
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return module
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load_module(f"{package_name}.sg13_tech", os.path.join(pcell_root, "sg13_tech.py"))
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sealring_module = load_module(
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f"{package_name}.ihp.sealring_code", os.path.join(ihp_root, "sealring_code.py")
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)
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tech = Tech.get("SG13_dev")
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Tech.techInUse = tech.getTechParams()["libName"]
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edge_box = float(re.sub("[a-zA-Z]+", "", tech.getTechParams()["sealring_complete_edgeBox"]))
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layout = pya.Layout(True)
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layout.dbu = 0.001
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top_cell = layout.create_cell("sealring_top")
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sealring = sealring_module.sealring()
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sealring.setTech(tech)
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with PyCellContext(tech, top_cell, sealring):
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sealring.addCellContext(top_cell)
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sealring.setupParams(
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{
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"l": f"{float(width) - 2 * edge_box}u",
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"w": f"{float(height) - 2 * edge_box}u",
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"addLabel": "nil",
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"addSlit": "nil",
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"edgeBox": f"{edge_box}u",
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}
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)
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sealring.genLayout()
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pathlib.Path(output).parent.mkdir(parents=True, exist_ok=True)
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options = pya.SaveLayoutOptions()
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options.write_context_info = False
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layout.write(output, options)

scripts/setup_technology.sh

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Original file line numberDiff line numberDiff line change
@@ -55,6 +55,14 @@ link_public_bondpad_gds() {
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done
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}
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link_cmos5l_klayout_dependencies() {
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local shared_pdk="$repo_root/ihp13/sg13g2/ihp-sg13g2"
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local upstream_layout="$repo_root/ihp13/ihp-sg13g2"
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[[ ! -d "$shared_pdk" || -e "$upstream_layout" || -L "$upstream_layout" ]] && return 0
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ln -s "sg13g2/ihp-sg13g2" "$upstream_layout"
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}
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prepare_public_verilator_stdcell() {
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local upstream_stdcell="$public_pdk/verilog/sg13g2_stdcell_upstream.v"
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local verilator_patch="$repo_root/ihp13/patches/0002-add-verilator-standard-cell-compatibility.patch"
@@ -82,6 +90,7 @@ create_public_technology_link() {
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}
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create_public_technology_link
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link_cmos5l_klayout_dependencies
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if [[ -e "$technology" ]]; then
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log "[INFO] Active technology view: $technology"

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