diff --git a/Bender.lock b/Bender.lock
index fb3c8c8d6..849163e81 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -25,7 +25,8 @@ packages:
     version: null
     source:
       Path: rtl/cve2
-    dependencies: []
+    dependencies:
+    - common_cells
   idma:
     revision: null
     version: null
diff --git a/Bender.yml b/Bender.yml
index 89e2ecdfc..c7253b242 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -69,7 +69,7 @@ sources:
       - rtl/test/croc_vip.sv
       - rtl/test/tb_croc_soc.sv
 
-  - target: genesys2
+  - target: any(genesys2, basys3)
     files:
       - xilinx/hw/croc_xilinx.sv
       - xilinx/hw/fan_ctrl.sv
diff --git a/xilinx/hw/croc_xilinx.sv b/xilinx/hw/croc_xilinx.sv
index af379e72f..a60b0f853 100644
--- a/xilinx/hw/croc_xilinx.sv
+++ b/xilinx/hw/croc_xilinx.sv
@@ -10,6 +10,7 @@
 // Philippe Sauter <phsauter@iis.ee.ethz.ch>
 
 `ifdef TARGET_GENESYS2
+  `define USE_DIFFERENTIAL_CLOCK
   `define USE_RESETN
   `define USE_JTAG_TRSTN
   `define USE_STATUS
@@ -19,6 +20,14 @@
   `define USE_VIO
 `endif
 
+`ifdef TARGET_BASYS3
+  `define USE_RESET
+  `define USE_STATUS
+  `define USE_SWITCHES
+  `define USE_LEDS
+  `define USE_VIO
+`endif
+
 `define ILA(__name, __signal)  \
   (* dont_touch = "yes" *) (* mark_debug = "true" *) logic [$bits(__signal)-1:0] __name; \
   assign __name = __signal;
@@ -27,7 +36,9 @@ module croc_xilinx import croc_pkg::*; #(
   localparam int unsigned GpioCount = 4
 ) (
   input  logic  sys_clk_p,
+`ifdef USE_DIFFERENTIAL_CLOCK
   input  logic  sys_clk_n,
+`endif
 
 `ifdef USE_RESET
   input  logic  sys_reset,
@@ -48,6 +59,7 @@ module croc_xilinx import croc_pkg::*; #(
   output logic   status_o,
 `endif
 
+`ifndef TARGET_BASYS3
   input  logic  jtag_tck_i,
   input  logic  jtag_tms_i,
   input  logic  jtag_tdi_i,
@@ -59,6 +71,7 @@ module croc_xilinx import croc_pkg::*; #(
   output logic  jtag_vdd_o,
   output logic  jtag_gnd_o,
 `endif
+`endif // TARGET_BASYS3
 
 `ifdef USE_FAN
   input  logic [2:0]  fan_sw, // switch 4-6
@@ -76,6 +89,7 @@ module croc_xilinx import croc_pkg::*; #(
   wire sys_clk;
   wire soc_clk;
 
+`ifdef USE_DIFFERENTIAL_CLOCK
   IBUFDS #(
     .IBUF_LOW_PWR ("FALSE")
   ) i_bufds_sys_clk (
@@ -83,6 +97,14 @@ module croc_xilinx import croc_pkg::*; #(
     .IB ( sys_clk_n ),
     .O  ( sys_clk   )
   );
+`else
+  IBUF #(
+    .IBUF_LOW_PWR ("FALSE")
+  ) i_buf_sys_clk (
+    .I  ( sys_clk_p ),
+    .O  ( sys_clk   )
+  );
+`endif
 
   clkwiz i_clkwiz (
     .clk_in1  ( sys_clk ),
@@ -177,6 +199,14 @@ module croc_xilinx import croc_pkg::*; #(
   //  JTAG  //
   ////////////
 
+`ifdef TARGET_BASYS3
+  // BSCANE2 mode: no external pins; dmi_bscane_tap drives through config JTAG
+  logic jtag_tck_i, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, jtag_trst_ni;
+  assign jtag_tck_i   = '0;
+  assign jtag_tms_i   = '0;
+  assign jtag_tdi_i   = '0;
+  assign jtag_trst_ni = '1;
+`else
 `ifdef USE_JTAG_VDDGND
   assign jtag_vdd_o = 1'b1;
   assign jtag_gnd_o = 1'b0;
@@ -185,6 +215,7 @@ module croc_xilinx import croc_pkg::*; #(
   logic jtag_trst_ni;
   assign jtag_trst_ni = 1'b1;
 `endif
+`endif // TARGET_BASYS3
 
 
   /////////////////////////
diff --git a/xilinx/run_xilinx.sh b/xilinx/run_xilinx.sh
index 73478b68b..6b9dd1fa3 100755
--- a/xilinx/run_xilinx.sh
+++ b/xilinx/run_xilinx.sh
@@ -17,13 +17,15 @@ set -u  # Error on undefined vars
 # Source environment
 source "../env.sh"
 
-VIVADO=${VIVADO:-"vitis-2022.1 vivado"}
+# Select IIS-internal tool commands if we run on IIS machines
+if [ -f /etc/iis.version ]; then
+    VIVADO=${VIVADO:-"vitis-2022.1 vivado"}
+else
+    VIVADO=${VIVADO:-"vivado"}
+fi
 
 mkdir -p build
 mkdir -p out
-mkdir -p build/genesys2.clkwiz
-mkdir -p build/genesys2.vio
-mkdir -p build/genesys2.croc
 
 
 ################
@@ -38,17 +40,19 @@ Usage:
     ./run_xilinx.sh [OPTIONS]
 
 Options:
-    --help, -h          Show this help message
-    --dry-run, -n       Only print commands instead of executing
-    --verbose, -v       Print commands while executing
-    --flist             Regenerate compile script reading sources (add_sources.genesys2.tcl)
-    --clkwiz            Implement build/genesys2.clkwiz
-    --vio               Implement build/genesys2.vio
-    --croc              Implement Croc SoC only
-    --all               Implement clkwiz, vio, and Croc SoC
+    --help, -h              Show this help message
+    --dry-run, -n           Only print commands instead of executing
+    --verbose, -v           Print commands while executing
+    --target <board>        Target board: genesys2 (default), basys3
+    --flist                 Regenerate compile script reading sources
+    --clkwiz                Implement clock wizard IP
+    --vio                   Implement VirtualIO IP
+    --croc                  Implement Croc SoC only
+    --all                   Implement clkwiz, vio, and Croc SoC
 
 Example:
     ./run_xilinx.sh --all
+    ./run_xilinx.sh --target basys3 --all
 
 EOF
     exit 0
@@ -64,45 +68,64 @@ run_cmd() {
 }
 
 
+get_bender_target() {
+    echo "$TARGET"
+}
+
+
 generate_flist() {
-    run_cmd "echo [INFO][Bender] Generate add_sources.genesys2.tcl"
+    local bender_target
+    bender_target=$(get_bender_target)
+
+    # Basys3 uses BSCANE2 for JTAG: pass 'xilinx' and 'bscane' so that
+    # riscv-dbg selects dmi_bscane_tap.sv instead of dmi_jtag_tap.sv.
+    local extra_targets=""
+    if [ "$TARGET" = "basys3" ]; then
+        extra_targets="-t xilinx -t bscane"
+    fi
+
+    run_cmd "echo [INFO][Bender] Generate add_sources.${TARGET}.tcl"
     run_cmd "bender \
         script vivado \
-        -t genesys2 \
+        -t ${bender_target} \
         -t synthesis \
+        ${extra_targets} \
         -D COMMON_CELLS_ASSERTS_OFF=1 \
-        > scripts/add_sources.genesys2.tcl"
+        > scripts/add_sources.${TARGET}.tcl"
 
     run_cmd "echo [INFO][Bender] Remove absolute paths"
-    run_cmd "sed -i 's|${CROC_ROOT}|../../..|g' scripts/add_sources.genesys2.tcl"
+    run_cmd "sed -i 's|${CROC_ROOT}|../../..|g' scripts/add_sources.${TARGET}.tcl"
 
-    run_cmd "echo [INFO][Bender] File list generated: add_sources.genesys2.tcl"
+    run_cmd "echo [INFO][Bender] File list generated: add_sources.${TARGET}.tcl"
 }
 
 
 impl_clockwiz() {
-    run_cmd "echo [INFO][VIVADO] Implement clock wizard IP"
-    run_cmd "cd build/genesys2.clkwiz"
+    mkdir -p build/${TARGET}.clkwiz
+    run_cmd "echo [INFO][VIVADO] Implement clock wizard IP [${TARGET}]"
+    run_cmd "cd build/${TARGET}.clkwiz"
     run_cmd "${VIVADO} -mode batch -source ../../scripts/impl_ip.tcl \
-        -tclargs genesys2 clkwiz > ../../clkwiz.log"
+        -tclargs ${TARGET} clkwiz > ../../clkwiz.${TARGET}.log"
     run_cmd "cd ../.."
 }
 
 
 impl_vio() {
-    run_cmd "echo [INFO][VIVADO] Implement VirtualIO IP"
-    run_cmd "cd build/genesys2.vio"
+    mkdir -p build/${TARGET}.vio
+    run_cmd "echo [INFO][VIVADO] Implement VirtualIO IP [${TARGET}]"
+    run_cmd "cd build/${TARGET}.vio"
     run_cmd "${VIVADO} -mode batch -source ../../scripts/impl_ip.tcl \
-        -tclargs genesys2 vio > ../../vio.log"
+        -tclargs ${TARGET} vio > ../../vio.${TARGET}.log"
     run_cmd "cd ../.."
 }
 
 
-impl_croc(){
-    run_cmd "echo [INFO][VIVADO] Implement Croc"
-    run_cmd "cd build/genesys2.croc"
+impl_croc() {
+    mkdir -p build/${TARGET}.croc
+    run_cmd "echo [INFO][VIVADO] Implement Croc [${TARGET}]"
+    run_cmd "cd build/${TARGET}.croc"
     run_cmd "${VIVADO} -mode batch -source ../../scripts/impl_sys.tcl \
-        -tclargs genesys2 croc ../genesys2.clkwiz/out.xci ../genesys2.vio/out.xci  > ../../croc.log"
+        -tclargs ${TARGET} croc ../${TARGET}.clkwiz/out.xci ../${TARGET}.vio/out.xci > ../../croc.${TARGET}.log"
     run_cmd "cd ../.."
 }
 
@@ -112,6 +135,7 @@ impl_croc(){
 ####################
 
 DRYRUN=0
+TARGET="genesys2"
 
 # default action if no argument is given
 if [ $# -eq 0 ]; then
@@ -119,10 +143,12 @@ if [ $# -eq 0 ]; then
     return 0
 fi
 
-# check for global arguments
-for arg in "$@"; do
-    [[ "$arg" == -v || "$arg" == --verbose ]] && set -x
-    [[ "$arg" == -n || "$arg" == --dry-run ]] && DRYRUN=1
+# check for global arguments (first pass, order-independent)
+args=("$@")
+for ((i=0; i<${#args[@]}; i++)); do
+    [[ "${args[i]}" == -v || "${args[i]}" == --verbose ]] && set -x
+    [[ "${args[i]}" == -n || "${args[i]}" == --dry-run ]] && DRYRUN=1
+    [[ "${args[i]}" == --target ]] && TARGET="${args[i+1]}"
 done
 
 # parse arguments
@@ -137,6 +163,10 @@ while [[ $# -gt 0 ]]; do
         --dry-run|-n)
             shift
             ;;
+        --target)
+            TARGET="$2"
+            shift 2
+            ;;
         # script-specific commands
         --flist)
             generate_flist
@@ -155,6 +185,7 @@ while [[ $# -gt 0 ]]; do
             shift
             ;;
         --all)
+            generate_flist
             impl_clockwiz
             impl_vio
             impl_croc
diff --git a/xilinx/scripts/add_sources.basys3.tcl b/xilinx/scripts/add_sources.basys3.tcl
new file mode 100644
index 000000000..0b5249de8
--- /dev/null
+++ b/xilinx/scripts/add_sources.basys3.tcl
@@ -0,0 +1,252 @@
+# This script was generated automatically by bender.
+set ROOT "../../.."
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/tech_cells_generic/fpga/pad_functional_xilinx.sv \
+    $ROOT/rtl/tech_cells_generic/fpga/tc_clk_xilinx.sv \
+    $ROOT/rtl/tech_cells_generic/fpga/tc_sram_xilinx.sv \
+    $ROOT/rtl/tech_cells_generic/tc_sram_impl.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/common_cells/binary_to_gray.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/common_cells/cb_filter_pkg.sv \
+    $ROOT/rtl/common_cells/cc_onehot.sv \
+    $ROOT/rtl/common_cells/cdc_reset_ctrlr_pkg.sv \
+    $ROOT/rtl/common_cells/cf_math_pkg.sv \
+    $ROOT/rtl/common_cells/clk_int_div.sv \
+    $ROOT/rtl/common_cells/credit_counter.sv \
+    $ROOT/rtl/common_cells/delta_counter.sv \
+    $ROOT/rtl/common_cells/ecc_pkg.sv \
+    $ROOT/rtl/common_cells/edge_propagator_tx.sv \
+    $ROOT/rtl/common_cells/exp_backoff.sv \
+    $ROOT/rtl/common_cells/fifo_v3.sv \
+    $ROOT/rtl/common_cells/gray_to_binary.sv \
+    $ROOT/rtl/common_cells/heaviside.sv \
+    $ROOT/rtl/common_cells/isochronous_4phase_handshake.sv \
+    $ROOT/rtl/common_cells/isochronous_spill_register.sv \
+    $ROOT/rtl/common_cells/lfsr.sv \
+    $ROOT/rtl/common_cells/lfsr_16bit.sv \
+    $ROOT/rtl/common_cells/lfsr_8bit.sv \
+    $ROOT/rtl/common_cells/lossy_valid_to_stream.sv \
+    $ROOT/rtl/common_cells/mv_filter.sv \
+    $ROOT/rtl/common_cells/onehot_to_bin.sv \
+    $ROOT/rtl/common_cells/plru_tree.sv \
+    $ROOT/rtl/common_cells/passthrough_stream_fifo.sv \
+    $ROOT/rtl/common_cells/popcount.sv \
+    $ROOT/rtl/common_cells/ring_buffer.sv \
+    $ROOT/rtl/common_cells/rr_arb_tree.sv \
+    $ROOT/rtl/common_cells/rstgen_bypass.sv \
+    $ROOT/rtl/common_cells/serial_deglitch.sv \
+    $ROOT/rtl/common_cells/shift_reg.sv \
+    $ROOT/rtl/common_cells/shift_reg_gated.sv \
+    $ROOT/rtl/common_cells/spill_register_flushable.sv \
+    $ROOT/rtl/common_cells/stream_demux.sv \
+    $ROOT/rtl/common_cells/stream_filter.sv \
+    $ROOT/rtl/common_cells/stream_fork.sv \
+    $ROOT/rtl/common_cells/stream_intf.sv \
+    $ROOT/rtl/common_cells/stream_join_dynamic.sv \
+    $ROOT/rtl/common_cells/stream_mux.sv \
+    $ROOT/rtl/common_cells/stream_throttle.sv \
+    $ROOT/rtl/common_cells/sub_per_hash.sv \
+    $ROOT/rtl/common_cells/sync.sv \
+    $ROOT/rtl/common_cells/sync_wedge.sv \
+    $ROOT/rtl/common_cells/unread.sv \
+    $ROOT/rtl/common_cells/read.sv \
+    $ROOT/rtl/common_cells/addr_decode_dync.sv \
+    $ROOT/rtl/common_cells/boxcar.sv \
+    $ROOT/rtl/common_cells/cdc_2phase.sv \
+    $ROOT/rtl/common_cells/cdc_4phase.sv \
+    $ROOT/rtl/common_cells/clk_int_div_static.sv \
+    $ROOT/rtl/common_cells/trip_counter.sv \
+    $ROOT/rtl/common_cells/addr_decode.sv \
+    $ROOT/rtl/common_cells/addr_decode_napot.sv \
+    $ROOT/rtl/common_cells/multiaddr_decode.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/common_cells/cb_filter.sv \
+    $ROOT/rtl/common_cells/cdc_fifo_2phase.sv \
+    $ROOT/rtl/common_cells/clk_mux_glitch_free.sv \
+    $ROOT/rtl/common_cells/counter.sv \
+    $ROOT/rtl/common_cells/ecc_decode.sv \
+    $ROOT/rtl/common_cells/ecc_encode.sv \
+    $ROOT/rtl/common_cells/edge_detect.sv \
+    $ROOT/rtl/common_cells/lzc.sv \
+    $ROOT/rtl/common_cells/max_counter.sv \
+    $ROOT/rtl/common_cells/rstgen.sv \
+    $ROOT/rtl/common_cells/spill_register.sv \
+    $ROOT/rtl/common_cells/stream_delay.sv \
+    $ROOT/rtl/common_cells/stream_fifo.sv \
+    $ROOT/rtl/common_cells/stream_fork_dynamic.sv \
+    $ROOT/rtl/common_cells/stream_join.sv \
+    $ROOT/rtl/common_cells/cdc_reset_ctrlr.sv \
+    $ROOT/rtl/common_cells/cdc_fifo_gray.sv \
+    $ROOT/rtl/common_cells/fall_through_register.sv \
+    $ROOT/rtl/common_cells/id_queue.sv \
+    $ROOT/rtl/common_cells/stream_to_mem.sv \
+    $ROOT/rtl/common_cells/stream_arbiter_flushable.sv \
+    $ROOT/rtl/common_cells/stream_fifo_optimal_wrap.sv \
+    $ROOT/rtl/common_cells/stream_register.sv \
+    $ROOT/rtl/common_cells/stream_xbar.sv \
+    $ROOT/rtl/common_cells/cdc_fifo_gray_clearable.sv \
+    $ROOT/rtl/common_cells/cdc_2phase_clearable.sv \
+    $ROOT/rtl/common_cells/mem_to_banks_detailed.sv \
+    $ROOT/rtl/common_cells/stream_arbiter.sv \
+    $ROOT/rtl/common_cells/stream_omega_net.sv \
+    $ROOT/rtl/common_cells/mem_to_banks.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/obi/obi_pkg.sv \
+    $ROOT/rtl/obi/obi_intf.sv \
+    $ROOT/rtl/obi/obi_rready_converter.sv \
+    $ROOT/rtl/obi/apb_to_obi.sv \
+    $ROOT/rtl/obi/obi_to_apb.sv \
+    $ROOT/rtl/obi/obi_atop_resolver.sv \
+    $ROOT/rtl/obi/obi_cut.sv \
+    $ROOT/rtl/obi/obi_demux.sv \
+    $ROOT/rtl/obi/obi_err_sbr.sv \
+    $ROOT/rtl/obi/obi_mux.sv \
+    $ROOT/rtl/obi/obi_sram_shim.sv \
+    $ROOT/rtl/obi/obi_xbar.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/apb/apb_pkg.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/cve2/cve2_pkg.sv \
+    $ROOT/rtl/cve2/cve2_alu.sv \
+    $ROOT/rtl/cve2/cve2_branch_predict.sv \
+    $ROOT/rtl/cve2/cve2_compressed_decoder.sv \
+    $ROOT/rtl/cve2/cve2_controller.sv \
+    $ROOT/rtl/cve2/cve2_counter.sv \
+    $ROOT/rtl/cve2/cve2_csr.sv \
+    $ROOT/rtl/cve2/cve2_decoder.sv \
+    $ROOT/rtl/cve2/cve2_fetch_fifo.sv \
+    $ROOT/rtl/cve2/cve2_load_store_unit.sv \
+    $ROOT/rtl/cve2/cve2_multdiv_fast.sv \
+    $ROOT/rtl/cve2/cve2_multdiv_slow.sv \
+    $ROOT/rtl/cve2/cve2_pmp.sv \
+    $ROOT/rtl/cve2/cve2_register_file_ff.sv \
+    $ROOT/rtl/cve2/cve2_wb.sv \
+    $ROOT/rtl/cve2/cve2_cs_registers.sv \
+    $ROOT/rtl/cve2/cve2_ex_block.sv \
+    $ROOT/rtl/cve2/cve2_id_stage.sv \
+    $ROOT/rtl/cve2/cve2_prefetch_buffer.sv \
+    $ROOT/rtl/cve2/cve2_if_stage.sv \
+    $ROOT/rtl/cve2/cve2_core.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/idma/idma_pkg.sv \
+    $ROOT/rtl/idma/idma_channel_coupler.sv \
+    $ROOT/rtl/idma/idma_dataflow_element.sv \
+    $ROOT/rtl/idma/idma_obi_read.sv \
+    $ROOT/rtl/idma/idma_obi_write.sv \
+    $ROOT/rtl/idma/idma_nd_midend.sv \
+    $ROOT/rtl/idma/idma_transfer_id_gen.sv \
+    $ROOT/rtl/idma/idma_legalizer_page_splitter.sv \
+    $ROOT/rtl/idma/idma_transport_layer_rw_obi.sv \
+    $ROOT/rtl/idma/idma_legalizer_rw_obi.sv \
+    $ROOT/rtl/idma/idma_backend_rw_obi.sv \
+    $ROOT/rtl/idma/croc_idma.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/obi_uart/obi_uart_pkg.sv \
+    $ROOT/rtl/obi_uart/obi_uart_baudgen.sv \
+    $ROOT/rtl/obi_uart/obi_uart_interrupts.sv \
+    $ROOT/rtl/obi_uart/obi_uart_modem.sv \
+    $ROOT/rtl/obi_uart/obi_uart_rx.sv \
+    $ROOT/rtl/obi_uart/obi_uart_tx.sv \
+    $ROOT/rtl/obi_uart/obi_uart_register.sv \
+    $ROOT/rtl/obi_uart/obi_uart.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/riscv-dbg/dm_pkg.sv \
+    $ROOT/rtl/riscv-dbg/debug_rom/debug_rom.sv \
+    $ROOT/rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv \
+    $ROOT/rtl/riscv-dbg/dm_csrs.sv \
+    $ROOT/rtl/riscv-dbg/dm_mem.sv \
+    $ROOT/rtl/riscv-dbg/dmi_cdc.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/riscv-dbg/dmi_bscane_tap.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/riscv-dbg/dm_sba.sv \
+    $ROOT/rtl/riscv-dbg/dm_top.sv \
+    $ROOT/rtl/riscv-dbg/dmi_jtag.sv \
+    $ROOT/rtl/riscv-dbg/dm_obi_top.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/croc_pkg.sv \
+    $ROOT/rtl/user_pkg.sv \
+    $ROOT/rtl/soc_ctrl/soc_ctrl_regs_pkg.sv \
+    $ROOT/rtl/gpio/gpio_reg_pkg.sv \
+    $ROOT/rtl/clint/clint_reg_pkg.sv \
+    $ROOT/rtl/obi_timer/obi_timer_reg_pkg.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/core_wrap.sv \
+    $ROOT/rtl/bootrom/bootrom.sv \
+    $ROOT/rtl/soc_ctrl/soc_ctrl_regs.sv \
+    $ROOT/rtl/gpio/gpio_reg_top.sv \
+    $ROOT/rtl/gpio/gpio.sv \
+    $ROOT/rtl/clint/clint.sv \
+    $ROOT/rtl/obi_timer/obi_timer.sv \
+    $ROOT/rtl/croc_domain.sv \
+    $ROOT/rtl/user_domain.sv \
+    $ROOT/rtl/croc_soc.sv \
+]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/xilinx/hw/croc_xilinx.sv \
+    $ROOT/xilinx/hw/fan_ctrl.sv \
+]
+
+set_property include_dirs [list \
+    $ROOT/rtl/apb/include \
+    $ROOT/rtl/common_cells/include \
+    $ROOT/rtl/cve2/include \
+    $ROOT/rtl/idma/include \
+    $ROOT/rtl/obi/include \
+] [current_fileset]
+
+set_property include_dirs [list \
+    $ROOT/rtl/apb/include \
+    $ROOT/rtl/common_cells/include \
+    $ROOT/rtl/cve2/include \
+    $ROOT/rtl/idma/include \
+    $ROOT/rtl/obi/include \
+] [current_fileset -simset]
+
+set_property verilog_define [list \
+    TARGET_BASYS3 \
+    TARGET_FPGA \
+    TARGET_SYNTHESIS \
+    TARGET_VIVADO \
+    TARGET_XILINX \
+    COMMON_CELLS_ASSERTS_OFF=1 \
+] [current_fileset]
+
+set_property verilog_define [list \
+    TARGET_BASYS3 \
+    TARGET_FPGA \
+    TARGET_SYNTHESIS \
+    TARGET_VIVADO \
+    TARGET_XILINX \
+    COMMON_CELLS_ASSERTS_OFF=1 \
+] [current_fileset -simset]
+
diff --git a/xilinx/scripts/common.tcl b/xilinx/scripts/common.tcl
index 0fcd14a95..0df2445f1 100644
--- a/xilinx/scripts/common.tcl
+++ b/xilinx/scripts/common.tcl
@@ -9,6 +9,12 @@ set bpart(genesys2) "digilentinc.com:genesys2:part0:1.1"
 set fpart(genesys2) "xc7k325tffg900-2"
 set hwdev(genesys2) "xc7k325t_0"
 
+# basys3 board params
+set bpart(basys3) "digilentinc.com:basys3:part0:1.2"
+set fpart(basys3) "xc7a35tcpg236-1"
+set hwdev(basys3) "xc7a35t_0"
+set cfgmp(basys3) "s25fl032p-spi-x1_x2_x4"
+
 # vcu128 board params
 set bpart(vcu128) "xilinx.com:vcu128:part0:1.0"
 set fpart(vcu128) "xcvu37p-fsvh2892-2L-e"
diff --git a/xilinx/scripts/impl_ip.tcl b/xilinx/scripts/impl_ip.tcl
index 5914548e3..6f55a7eec 100644
--- a/xilinx/scripts/impl_ip.tcl
+++ b/xilinx/scripts/impl_ip.tcl
@@ -15,10 +15,11 @@ init_impl $xilinx_root $argc $argv
 switch $proj {
 
     clkwiz {
+        set prim_in_freq [expr { $board eq "basys3" ? "100.000" : "200.000" }]
         create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name $proj
         set_property -dict [list \
             CONFIG.PRIM_SOURCE {No_buffer} \
-            CONFIG.PRIM_IN_FREQ {200.000} \
+            CONFIG.PRIM_IN_FREQ $prim_in_freq \
             CONFIG.CLKOUT1_USED {true} \
             CONFIG.CLK_OUT1_PORT {clk_20} \
             CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {20.000} \
diff --git a/xilinx/scripts/openocd.basys3.tcl b/xilinx/scripts/openocd.basys3.tcl
new file mode 100644
index 000000000..db3b5b730
--- /dev/null
+++ b/xilinx/scripts/openocd.basys3.tcl
@@ -0,0 +1,61 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# OpenOCD script for CROC on Basys3 via Xilinx BSCANE2 (USER3/USER4 chains).
+#
+# JTAG is tunnelled through the FPGA's built-in config JTAG using dmi_bscane_tap.
+# No external JTAG pins or probe cable are required.
+#
+# Requirements:
+#   - riscv-openocd (or upstream OpenOCD >= 0.12 with RISC-V target support)
+#   - Vivado hw_server must NOT be holding the USB-JTAG interface while this runs
+#
+# Usage:
+#   openocd -f openocd.basys3.tcl
+#
+# If the adapter is not found, check the VID/PID with 'lsusb'. Digilent boards
+# sometimes enumerate as 0x0403/0x6014 instead of 0x0403/0x6010.
+
+adapter speed 1000
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+ftdi layout_init 0x00e8 0x60eb
+ftdi channel 0
+
+transport select jtag
+telnet_port disabled
+tcl_port disabled
+reset_config none
+
+# Only physical TAP in the chain: Artix-7 35T config JTAG (6-bit IR)
+jtag newtap xc7 tap -irlen 6 -ignore-version -expected-id 0x0362d093
+
+set _TARGETNAME riscv_cpu
+target create $_TARGETNAME riscv -chain-position xc7.tap -coreid 0
+
+# Route RISC-V debug accesses through the BSCANE2 USER chains:
+#   DTMCS  ->  USER3 = IR 0x22  (BSCANE2 JTAG_CHAIN 3)
+#   DMI    ->  USER4 = IR 0x23  (BSCANE2 JTAG_CHAIN 4)
+riscv set_ir dtmcs 0x22
+riscv set_ir dmi   0x23
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+riscv set_command_timeout_sec 120
+# These are optional tuning knobs whose names vary across riscv-openocd
+# versions; wrap in catch so an unknown/removed command can't abort the script.
+catch { riscv set_reset_timeout_sec 120 }
+# 'set_prefer_sba off' was removed; the modern equivalent (try program-buffer
+# access before the system bus) is set_mem_access. Defaults are fine if absent.
+catch { riscv set_mem_access progbuf sysbus abstract }
+
+if { [catch { riscv set_enable_virtual on } ] } {
+    echo "Warning: This version of OpenOCD does not support address translation.\
+        To debug on virtual addresses, please update to the latest version."
+}
+
+init
+halt
+echo "Ready for Remote Connections"
diff --git a/xilinx/src/basys3.xdc b/xilinx/src/basys3.xdc
new file mode 100644
index 000000000..40946d1e9
--- /dev/null
+++ b/xilinx/src/basys3.xdc
@@ -0,0 +1,70 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Nicole Narr <narrn@student.ethz.ch>
+# Christopher Reinwardt <creinwar@student.ethz.ch>
+# Cyril Koenig <cykoenig@iis.ee.ethz.ch>
+# Paul Scheffler <paulsc@iis.ee.ethz.ch>
+
+#############
+# Sys Clock #
+#############
+
+# 100 MHz input clock
+set SYS_TCK 10
+create_clock -period $SYS_TCK -name sys_clk_p [get_ports sys_clk_p]
+
+# SoC clock is generated by clock wizard and its constraints
+set SOC_TCK 50.0
+set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_20]]
+
+############
+# Switches #
+############
+
+set_input_delay -min -clock $soc_clk [expr { $SOC_TCK * 0.10 }] [ \
+    get_ports {gpio_i*}]
+set_input_delay -max -clock $soc_clk [expr { $SOC_TCK * 0.35 }] [ \
+    get_ports {gpio_i*}]
+
+set_max_delay [expr { 2 * $SOC_TCK }] -from [get_ports {gpio_i*}]
+set_false_path -hold -from [get_ports {gpio_i*}]
+
+# LEDs
+set_output_delay -min -clock $soc_clk [expr { $SOC_TCK * 0.10 }] [get_ports gpio_o]
+set_output_delay -max -clock $soc_clk [expr { $SOC_TCK * 0.35 }] [get_ports gpio_o]
+
+
+###############
+# Assign Pins #
+###############
+
+# tclint-disable line-length, spacing
+
+## Clock Signal
+set_property -dict { PACKAGE_PIN W5    IOSTANDARD LVCMOS33 } [get_ports { sys_clk_p }]; 
+
+## Buttons
+set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { sys_reset }]; # CHECKME polarity
+
+## Switches
+set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { gpio_i[0] }]; # SW0
+set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { gpio_i[1] }]; # SW1
+set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { gpio_i[2] }]; # SW2
+set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports { gpio_i[3] }]; # SW3
+# set_property -dict { PACKAGE_PIN R2   IOSTANDARD LVCMOS33 } [get_ports { fetch_en_i }]; # SW15
+
+## LEDs
+set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { gpio_o[0] }]; # LD0
+set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports { gpio_o[1] }]; # LD1
+set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { gpio_o[2] }]; # LD2
+set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { gpio_o[3] }]; # LD3
+set_property -dict { PACKAGE_PIN L1   IOSTANDARD LVCMOS33 } [get_ports { status_o }]; # LD15
+
+## UART
+set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { uart_tx_o }];
+# set_property -dict { PACKAGE_PIN P1    IOSTANDARD LVCMOS33 } [get_ports { uart_tx_o }]; # LD14
+set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { uart_rx_i }];
+
+# tclint-enable line-length, spacing
\ No newline at end of file