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d1d1f6f
pdk: add IHP collateral sources
phsauter Jun 30, 2026
df7c003
pdk: use active technology view in flows
phsauter Jun 30, 2026
9fd9d4a
docs: document IHP PDK sources
phsauter Jun 30, 2026
8f4791b
pdk: simplify technology views and netlist simulation
phsauter Jul 20, 2026
f456643
pdk: vendor standard-cell source for Verilator
phsauter Jul 20, 2026
f3d02c4
pdk: complete cockpit technology view
phsauter Jul 20, 2026
9b4a14a
yosys: honor Bender file-list defines
phsauter Jul 21, 2026
c5dda91
pdk: fix public GDS streamout
phsauter Jul 21, 2026
3ea6736
ci: use RTL Verilator log
phsauter Jul 21, 2026
a33f418
ci: run idma tests with rebuilt model
phsauter Jul 21, 2026
8447062
ci: download public GDS before streamout
phsauter Jul 21, 2026
be11d0a
klayout: isolate seal-ring batch runs
phsauter Jul 21, 2026
eda4c2e
klayout: bootstrap seal-ring PCells explicitly
phsauter Jul 22, 2026
3babeed
klayout: generate seal rings without PCell registry
phsauter Jul 22, 2026
51ee93a
klayout: keep seal generation out of database mode
phsauter Jul 22, 2026
23b7b87
klayout: avoid Qt initialization for seal generation
phsauter Jul 22, 2026
c65b1cb
pdk: consolidate public collateral
phsauter Jul 22, 2026
9a34ab0
pdk: complete cockpit collateral links
phsauter Jul 22, 2026
1f21d31
pdk: check in Verilator standard cell model
phsauter Jul 27, 2026
81c3ab1
pdk: keep single patched standard cell model
phsauter Jul 27, 2026
f7ab37b
pdk: fix standard cell update
phsauter Jul 28, 2026
ec46523
sim: validate gate-level technology models
phsauter Jul 28, 2026
ebc4c8e
klayout: defer stream GDS validation
phsauter Jul 28, 2026
de6b824
pdk: centralize collateral updates
phsauter Jul 28, 2026
6e9bb9c
sim: validate JTAG after reset
phsauter Jul 29, 2026
250bab0
pdk: remove unused attributes
phsauter Jul 29, 2026
91b7ba7
pdk: simplify file descriptions
phsauter Jul 29, 2026
040993e
pdk: constrain manifest outputs
phsauter Jul 30, 2026
7e995e1
klayout: keep dry runs read-only
phsauter Jul 30, 2026
4054ea4
build: ignore Bender checkout
phsauter Jul 30, 2026
f265588
flow: preserve dry-run and compile failures
phsauter Jul 30, 2026
f9e9a61
flow: keep dry runs read-only
phsauter Jul 30, 2026
99ad645
verilator: preserve netlist dry runs
phsauter Jul 31, 2026
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76 changes: 59 additions & 17 deletions .cockpitrc
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,9 @@
# SG13G2_1.2.10
# SG13G2_1.2.13
# SG13G2_1.3.1
# SG13CMOS5L_1.3.1
# SG13CMOS5L_1.3.1 #--hacked version for experimental
# SG13CMOS5L_0.1
# SG13CMOS5L_0.2
#
# IO cell : ixc013g2_iocell_rev0.0.2
# ixc013g2_iocell_rev0.0.4
Expand All @@ -26,7 +28,8 @@
# ixc013g2_iocell_rev1.2.1
# open_io_v0.1
# open_io_v0.2
# sg13g2camos5l_io_v0.2
# sg13g2camos5l_io_v0.2 #--hacked version for experimental
# sg13cmos5l_io_v0.1
# bondpad : bondpad_70x70_v0
# bondpad5l_70x70_v0
#
Expand All @@ -42,32 +45,70 @@
# open_stdcell_v3.1
# open_stdcell_v3.2
# open_stdcell_rev0.1.3
# sg13cmos5l_stdcell_v0.1
# ez130_8t_stdcell_v0
# ez130_8t_stdcell_v0.12
# ez130_8t_stdcell_v1.0
# ez130_7t_stdcell_v0
#
# memories : RM_IHPSG13_v1.0
# RM_IHPSG13_v2.0
# open_sram_v2.0
# open_sram_v2.1
# open_sram_v2.2
#
# ip : agingsensor_v1.0
# agingsensor_v1.1
# agingsensor_v1.2
#

libs = SG13G2_1.3.1 \
libs = SG13CMOS5L_0.2 \
open_stdcell_rev0.1.3 \
open_io_v0.2 \
open_sram_v2.1
sg13cmos5l_stdcell_v0.1 \
sg13cmos5l_io_v0.1 \
SG13G2_1.3.1 \
ez130_8t_stdcell_v1.0 \
open_io_v0.2 \
open_sram_v2.2 \
bondpad5l_70x70_v0


macros = RM_IHPSG13_1P_1024x64_c2_bm_bist \
RM_IHPSG13_1P_2048x64_c2_bm_bist \
RM_IHPSG13_1P_256x48_c2_bm_bist \
RM_IHPSG13_1P_256x64_c2_bm_bist \
RM_IHPSG13_1P_512x64_c2_bm_bist \
RM_IHPSG13_1P_64x64_c2_bm_bist

# If you need other macros, add them to 'macros' below
# Don't forget the backslash to continue the line!
#
# Available macros area per bit [um^2/bit]
# -------------------------------------------------------
# RM_IHPSG13_1P_64x64_c2_bm_bist 12.3
# RM_IHPSG13_1P_256x8_c3_bm_bist 8.57
# RM_IHPSG13_1P_256x16_c2_bm_bist 6.87
# RM_IHPSG13_1P_256x32_c2_bm_bist 6.04
# RM_IHPSG13_1P_256x48_c2_bm_bist 5.77
# RM_IHPSG13_1P_256x64_c2_bm_bist 5.69
# RM_IHPSG13_1P_512x8_c3_bm_bist 6.38
# RM_IHPSG13_1P_512x16_c2_bm_bist 5.53
# RM_IHPSG13_1P_512x32_c2_bm_bist 4.87
# RM_IHPSG13_1P_512x64_c2_bm_bist 4.58
# RM_IHPSG13_1P_1024x8_c2_bm_bist 6.03
# RM_IHPSG13_1P_1024x16_c2_bm_bist 4.86
# RM_IHPSG13_1P_1024x32_c2_bm_bist 4.28
# RM_IHPSG13_1P_1024x64_c2_bm_bist 4.03
# RM_IHPSG13_1P_2048x64_c2_bm_bist 3.75
# RM_IHPSG13_1P_4096x8_c3_bm_bist 4.47
# RM_IHPSG13_1P_4096x16_c3_bm_bist 3.93
# RM_IHPSG13_1P_8192x32_c4 3.59
#
# RM_IHPSG13_2P_64x22_c2 28.0
# RM_IHPSG13_2P_64x32_c2 25.7
# RM_IHPSG13_2P_256x8_c2_bm_bist 18.6
# RM_IHPSG13_2P_256x16_c2_bm_bist 14.0
# RM_IHPSG13_2P_256x32_c2_bm_bist 11.8
# RM_IHPSG13_2P_512x8_c2_bm_bist 14.0
# RM_IHPSG13_2P_512x16_c2_bm_bist 10.8
# RM_IHPSG13_2P_512x32_c2_bm_bist 9.19
# RM_IHPSG13_2P_1024x16_c2_bm_bist 9.47
# RM_IHPSG13_2P_1024x32_c2_bm_bist 8.06

macros = RM_IHPSG13_1P_512x32_c2_bm_bist


[version]
Expand All @@ -89,8 +130,10 @@
innovus = innovus-21
dfii = ic-6
calibre = calibre-2021.3
oseda = oseda -2025.12

#this is actually the oseda version
klayout = klayout-2026.04

[command]
# Startup commands available through the GUI buttons.
# - startup commands can be modified but need to be compatible with the
Expand All @@ -107,8 +150,7 @@
innovus = xterm -g 136x40 -T innovus-21.13 -e "cds_innovus-21.13.000 innovus"
calibre = xterm -g 120x40 -T calibredrv-2021.3 -e "./start_calibre 2021.3"
dfii = ./start_dfii
yosys = xterm -g 120x40 -T yosys -e "oseda -2025.12 yosys -C"
openroad = xterm -g 120x40 -T openroad -e "oseda -2025.12 openroad -gui"
klayout = xterm -g 120x40 -T klayout -e "setenv KLAYOUT_HOME ./.klayout; oseda -2025.12 klayout -e"
yosys = xterm -g 120x40 -T yosys -e "oseda -2026.02 yosys -C"
openroad = xterm -g 120x40 -T openroad -e "oseda -2026.02 openroad -gui"
klayout = xterm -g 120x40 -T klayout -e "./start_klayout"
dz:llama = llama

5 changes: 5 additions & 0 deletions .github/scripts/run_full_flow.sh
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,11 @@ CROC_ROOT="$(cd "$SCRIPT_DIR/../.." && pwd)"

cd "$CROC_ROOT"

echo "============================================="
echo " Preparing public PDK GDS"
echo "============================================="
scripts/download_gds.sh

echo "============================================="
echo " Step 1: Yosys synthesis"
echo "============================================="
Expand Down
12 changes: 6 additions & 6 deletions .github/scripts/run_sim_flow.sh
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,9 @@ CROC_ROOT="$(cd "$SCRIPT_DIR/../.." && pwd)"

cd "$CROC_ROOT"

# Always restore the checked-in default after a configuration-specific run.
trap '"$SCRIPT_DIR/set_croc_config.sh"' EXIT

echo "============================================="
echo "Phase 1: default config — helloworld"
echo "============================================="
Expand All @@ -31,10 +34,10 @@ make -C sw
cd verilator
./run_verilator.sh --build
./run_verilator.sh --run ../sw/bin/helloworld.hex
grep -q "\[UART\] Hello World from Croc!" croc.log || exit 1
grep -q "\[UART\] Hello World from Croc!" croc_rtl.log || exit 1

./run_verilator.sh --run ../sw/bin/test/print_config.hex
"$SCRIPT_DIR/check_sim.sh" croc.log
"$SCRIPT_DIR/check_sim.sh" croc_rtl.log

cd "$CROC_ROOT"

Expand All @@ -51,12 +54,9 @@ cd verilator
./run_verilator.sh --build

# run all unit tests
"$SCRIPT_DIR/run_tests.sh"
"$SCRIPT_DIR/run_tests.sh" --sim obj_dir_rtl/Vtb_croc_soc
cd "$CROC_ROOT"

# restore defaults
"$SCRIPT_DIR/set_croc_config.sh"

echo ""
echo "============================================="
echo " Simulation completed"
Expand Down
2 changes: 1 addition & 1 deletion .github/workflows/short-flow.yml
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ jobs:
name: simulation-output
path: |
verilator/croc.fst
verilator/croc.log
verilator/croc_rtl.log
continue-on-error: true
- name: Upload test logs
uses: actions/upload-artifact@v4
Expand Down
89 changes: 87 additions & 2 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -1,3 +1,88 @@
.bender
tmp
# .gitignore files for cockpit

# all
/.bender/
*.20[0-9]*-[0-9]*-[0-9]*-[0-9]*:[0-9]*:[0-9]*
*.log
*.log[0-9]
*.log[0-9][0-9]
# cockpit root
/.llamaconfig
/tmp
/calibre
/docs
/technology
/.setPDK.csh
# public PDK mirror
/ihp13/pdk/gds/*.gds
!/ihp13/pdk/gds/bondpad_70x70.gds
!/ihp13/pdk/gds/bondpad5l_70x70.gds
# dfii
/dfii/
/dfii/.cdsinit
/dfii/.init
/dfii/.cadence
/dfii/.calibreviewsetup
/dfii/.simrc
/dfii/.tech
/dfii/.tmp_*
/dfii/start_dfii
/dfii/si.env
/dfii/*.cdslck*
/dfii/*/*/adexl/results
/dfii/*/*/adexl/test_states/*/*/spectre/*_Interactive.*
# innovus
/innovus/enc.tcl
/innovus/save
/innovus/out
/innovus/timingReports
/innovus/powerReports
/innovus/reports
/innovus/extLogDir
/innovus/work
/innovus/work_vs2api
/innovus/.AAE_*
/innovus/innovus.log*
/innovus/innovus.cmd*
/innovus/.interactive.constr.sdc
/innovus/.cadence
/innovus/scripts/add_clk_decaps.tcl
/innovus/scripts/checkdesign.tcl
/innovus/scripts/exportall.tcl
/innovus/scripts/fillperi-insert.tcl
/innovus/scripts/special_cell_setting.tcl
/innovus/src/sample
# synopsys
/synopsys/WORK
/synopsys/DDC
/synopsys/alib
/synopsys/reports
/synopsys/save
/synopsys/out
/synopsys/
/synopsys/default.svf
/synopsys/.synopsys_dc.setup
/synopsys/.synopsys_pt.setup
# sourcecode
# modelsim
/modelsim/README
/modelsim/work
/modelsim/*.csh-example
/modelsim/modelsim.ini
/modelsim/vcd
/modelsim/*.wlf
/modelsim/transcript
# tetramax
/tetramax/reports
/tetramax/tmaxtcl.rc
/tetramax/scripts/read_lib.tcl
/tetramax/scripts/tmax.tcl
# klayout
/klayout/*-example
/klayout/start_klayout
#openroad
/openroad/out
/openroad/save
#/openroad/src
#yosys
/yosys/out
9 changes: 6 additions & 3 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -1,6 +1,9 @@
[submodule "ihp13/pdk"]
path = ihp13/pdk
url = https://github.com/IHP-GmbH/IHP-Open-PDK
[submodule "artistic/artistic"]
path = artistic/artistic
url = git@github.com:pulp-platform/artistic.git
[submodule "ihp13/sg13cmos5l"]
path = ihp13/sg13cmos5l
url = https://github.com/IHP-GmbH/ihp-sg13cmos5l
[submodule "ihp13/sg13g2"]
path = ihp13/sg13g2
url = https://github.com/IHP-GmbH/IHP-Open-PDK
2 changes: 1 addition & 1 deletion Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ sources:
# Level 3
- rtl/croc_soc.sv

- target: not(fpga)
- target: all(not(fpga), not(netlist_yosys))
files:
# Level 0
- rtl/croc_chip.sv
Expand Down
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