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fix: add custom testbench
1 parent 81b17f1 commit 2aeb94a

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test/Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -170,11 +170,12 @@ vsim-clean:
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########## Verilator #############
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##################################
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VERILATOR_JOBS ?= 0
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VERILATOR_BUILD_DIR := $(VERILATOR_DIR)/build
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VERILATOR_LOG_DIR := $(VERILATOR_DIR)/logs
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VERILATOR_FLIST := $(VERILATOR_DIR)/cva6tb.flist
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VERILATOR_WARNINGS := -Wall -Wno-fatal -Wno-style -Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE -Wno-IMPLICITSTATIC
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VERILATOR_FLAGS := --binary -j 0 --Mdir $(VERILATOR_BUILD_DIR) $(VERILATOR_WARNINGS) -O3 -f $(VERILATOR_FLIST) --assert --timing \
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VERILATOR_FLAGS := --binary -j $(VERILATOR_JOBS) --Mdir $(VERILATOR_BUILD_DIR) $(VERILATOR_WARNINGS) -O3 -f $(VERILATOR_FLIST) --assert --timing \
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--trace-fst --trace-structs --trace-threads 2 --x-assign fast --x-initial fast
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$(VERILATOR_LOG_DIR):

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