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fix: add custom testbench
1 parent c1604b7 commit 81b17f1

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test/Makefile

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Original file line numberDiff line numberDiff line change
@@ -181,7 +181,7 @@ $(VERILATOR_LOG_DIR):
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@mkdir -p $(VERILATOR_LOG_DIR)
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$(VERILATOR_FLIST): $(ROOT_DIR)/Bender.lock $(HW_DEPS)
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$(BENDER) script verilator $(BENDER_FLAGS) -t verilator > $@
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$(BENDER) script verilator $(BENDER_FLAGS) -D ASSERTS_OFF -t verilator > $@
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$(VERILATOR_BUILD_DIR)/Vtest: $(VERILATOR_FLIST) | $(VERILATOR_LOG_DIR)
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cd $(VERILATOR_DIR) && $(VERILATOR) $(VERILATOR_FLAGS) --top-module test | tee $(VERILATOR_LOG_DIR)/build.log

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