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ezelioliezelioli
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feat(hwstack): fix verible linting
1 parent 85c4bea commit 8f6c0e0

7 files changed

Lines changed: 134 additions & 136 deletions

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‎core/controller.sv‎

Lines changed: 62 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -106,9 +106,9 @@ module controller
106106
// Address of trap vector table entry - CSR
107107
input logic [CVA6Cfg.VLEN-1:0] trap_vector_base_i,
108108
// Integer Register File content - ISSUE_STAGE
109-
input logic [31:0] [CVA6Cfg.XLEN-1:0] int_regs_i,
109+
input logic [31:0][CVA6Cfg.XLEN-1:0] int_regs_i,
110110
// Floating Point Register File content - ISSUE_STAGE
111-
input logic [31:0] [CVA6Cfg.XLEN-1:0] fp_regs_i,
111+
input logic [31:0][CVA6Cfg.XLEN-1:0] fp_regs_i,
112112
// Kernel stack pointer from CSR - CSR_REGFILE
113113
input logic [CVA6Cfg.XLEN-1:0] kernel_stack_pointer_i,
114114
// Write enable to integer register file for SP update - ISSUE_STAGE
@@ -282,45 +282,45 @@ module controller
282282

283283
// Hwstack fill FSM signals
284284
hwstack_fifo_fill_state_e hwstack_fill_state_d, hwstack_fill_state_q;
285-
logic [4:0] hwstack_regs_count_d, hwstack_regs_count_q;
286-
logic [4:0] hwstack_regs_num_d, hwstack_regs_num_q;
285+
logic [4:0] hwstack_regs_count_d, hwstack_regs_count_q;
286+
logic [4:0] hwstack_regs_num_d, hwstack_regs_num_q;
287287

288288
// Hwstack drain FSM signals
289-
hwstack_fifo_drain_state_e hwstack_drain_state_d, hwstack_drain_state_q;
290-
logic [CVA6Cfg.VLEN-1:0] hwstack_drain_address_d, hwstack_drain_address_q;
289+
hwstack_fifo_drain_state_e hwstack_drain_state_d, hwstack_drain_state_q;
290+
logic [CVA6Cfg.VLEN-1:0] hwstack_drain_address_d, hwstack_drain_address_q;
291291

292292
// Hwstack configuration
293293
logic [1:0] hwstack_config;
294294
logic [1:0] hwstack_config_d, hwstack_config_q;
295295

296-
logic [4:0] hwstack_regs_num;
297-
logic [31:0] [CVA6Cfg.XLEN-1:0] hwstack_reg_pool;
296+
logic [ 4:0] hwstack_regs_num;
297+
logic [ 31:0][CVA6Cfg.XLEN-1:0] hwstack_reg_pool;
298298

299299
// Hwstack FIFO control signals
300-
logic [CVA6Cfg.HwstackFifoDepth-1:0] [CVA6Cfg.XLEN-1:0] hwstack_fifo_load_data;
301-
logic [CVA6Cfg.XLEN-1:0] hwstack_fifo_wdata;
302-
logic [CVA6Cfg.XLEN-1:0] hwstack_fifo_rdata;
303-
logic hwstack_fifo_load;
304-
logic hwstack_fifo_full;
305-
logic hwstack_fifo_empty;
306-
logic hwstack_fifo_push;
307-
logic hwstack_fifo_pop;
300+
logic [CVA6Cfg.HwstackFifoDepth-1:0][CVA6Cfg.XLEN-1:0] hwstack_fifo_load_data;
301+
logic [ CVA6Cfg.XLEN-1:0] hwstack_fifo_wdata;
302+
logic [ CVA6Cfg.XLEN-1:0] hwstack_fifo_rdata;
303+
logic hwstack_fifo_load;
304+
logic hwstack_fifo_full;
305+
logic hwstack_fifo_empty;
306+
logic hwstack_fifo_push;
307+
logic hwstack_fifo_pop;
308308

309309
// Data cache request signals
310-
logic hwstack_dcache_req_valid;
310+
logic hwstack_dcache_req_valid;
311311

312-
assign dcache_req_o.data_req = hwstack_dcache_req_valid;
312+
assign dcache_req_o.data_req = hwstack_dcache_req_valid;
313313
assign dcache_req_o.address_index = hwstack_drain_address_q[CVA6Cfg.DCACHE_INDEX_WIDTH-1:0];
314314
assign dcache_req_o.address_tag = hwstack_drain_address_q[CVA6Cfg.DCACHE_TAG_WIDTH+CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_INDEX_WIDTH];
315-
assign dcache_req_o.data_wdata = hwstack_fifo_rdata;
316-
assign dcache_req_o.data_wuser = '0;
317-
assign dcache_req_o.data_we = 1'b1;
318-
assign dcache_req_o.data_be = '1;
319-
assign dcache_req_o.data_size = '1;
320-
assign dcache_req_o.data_id = '0;
321-
assign dcache_req_o.tag_valid = '0;
322-
assign dcache_req_o.kill_req = '0;
323-
assign dcache_req_o.cbo_op = '0;
315+
assign dcache_req_o.data_wdata = hwstack_fifo_rdata;
316+
assign dcache_req_o.data_wuser = '0;
317+
assign dcache_req_o.data_we = 1'b1;
318+
assign dcache_req_o.data_be = '1;
319+
assign dcache_req_o.data_size = '1;
320+
assign dcache_req_o.data_id = '0;
321+
assign dcache_req_o.tag_valid = '0;
322+
assign dcache_req_o.kill_req = '0;
323+
assign dcache_req_o.cbo_op = '0;
324324

325325
assign hwstack_fifo_wdata = hwstack_reg_pool[hwstack_regs_count_q];
326326

@@ -356,30 +356,31 @@ module controller
356356
hwstack_reg_pool = '0;
357357
hwstack_regs_num = '0;
358358
hwstack_regs_count_o = '0;
359-
case(hwstack_config)
359+
case (hwstack_config)
360360
2'b01: begin
361361
// Only caller-saved registers
362362
hwstack_regs_num = 5'd16;
363-
hwstack_reg_pool[ 0] = int_regs_i[ 1]; // ra
364-
hwstack_reg_pool[ 1] = int_regs_i[ 2]; // sp
365-
hwstack_reg_pool[ 2] = int_regs_i[ 5]; // t0
366-
hwstack_reg_pool[ 3] = int_regs_i[ 6]; // t1
367-
hwstack_reg_pool[ 4] = int_regs_i[ 7]; // t2
368-
hwstack_reg_pool[ 5] = int_regs_i[10]; // a0
369-
hwstack_reg_pool[ 6] = int_regs_i[11]; // a1
370-
hwstack_reg_pool[ 7] = int_regs_i[12]; // a2
371-
hwstack_reg_pool[ 8] = int_regs_i[13]; // a3
372-
hwstack_reg_pool[ 9] = int_regs_i[14]; // a4
373-
hwstack_reg_pool[10] = int_regs_i[15]; // a5
374-
hwstack_reg_pool[11] = int_regs_i[16]; // a6
375-
hwstack_reg_pool[12] = int_regs_i[17]; // a7
376-
hwstack_reg_pool[13] = int_regs_i[28]; // t3
377-
hwstack_reg_pool[14] = int_regs_i[29]; // t4
378-
hwstack_reg_pool[15] = int_regs_i[30]; // t5
379-
hwstack_reg_pool[16] = int_regs_i[31]; // t6
363+
hwstack_reg_pool[0] = int_regs_i[1]; // ra
364+
hwstack_reg_pool[1] = int_regs_i[2]; // sp
365+
hwstack_reg_pool[2] = int_regs_i[5]; // t0
366+
hwstack_reg_pool[3] = int_regs_i[6]; // t1
367+
hwstack_reg_pool[4] = int_regs_i[7]; // t2
368+
hwstack_reg_pool[5] = int_regs_i[10]; // a0
369+
hwstack_reg_pool[6] = int_regs_i[11]; // a1
370+
hwstack_reg_pool[7] = int_regs_i[12]; // a2
371+
hwstack_reg_pool[8] = int_regs_i[13]; // a3
372+
hwstack_reg_pool[9] = int_regs_i[14]; // a4
373+
hwstack_reg_pool[10] = int_regs_i[15]; // a5
374+
hwstack_reg_pool[11] = int_regs_i[16]; // a6
375+
hwstack_reg_pool[12] = int_regs_i[17]; // a7
376+
hwstack_reg_pool[13] = int_regs_i[28]; // t3
377+
hwstack_reg_pool[14] = int_regs_i[29]; // t4
378+
hwstack_reg_pool[15] = int_regs_i[30]; // t5
379+
hwstack_reg_pool[16] = int_regs_i[31]; // t6
380380
if (hwstack_fill_state_q != HWSTACK_FILL_IDLE) begin
381381
hwstack_regs_count_o = get_abi_index(hwstack_regs_count_q);
382-
end;
382+
end
383+
;
383384
end
384385
2'b10: begin
385386
// All GPRs
@@ -391,18 +392,18 @@ module controller
391392
end
392393

393394
hwstack_fifo #(
394-
.CVA6Cfg ( CVA6Cfg )
395+
.CVA6Cfg(CVA6Cfg)
395396
) i_hwstack_fifo (
396-
.clk_i ( clk_i ),
397-
.rst_ni ( rst_ni ),
398-
.load_i ( hwstack_fifo_load ),
399-
.load_data_i ( hwstack_fifo_load_data ),
400-
.data_i ( hwstack_fifo_wdata ),
401-
.push_i ( hwstack_fifo_push ),
402-
.pop_i ( hwstack_fifo_pop ),
403-
.data_o ( hwstack_fifo_rdata ),
404-
.empty_o ( hwstack_fifo_empty ),
405-
.full_o ( hwstack_fifo_full )
397+
.clk_i (clk_i),
398+
.rst_ni (rst_ni),
399+
.load_i (hwstack_fifo_load),
400+
.load_data_i(hwstack_fifo_load_data),
401+
.data_i (hwstack_fifo_wdata),
402+
.push_i (hwstack_fifo_push),
403+
.pop_i (hwstack_fifo_pop),
404+
.data_o (hwstack_fifo_rdata),
405+
.empty_o (hwstack_fifo_empty),
406+
.full_o (hwstack_fifo_full)
406407
);
407408

408409
always_ff @(posedge clk_i or negedge rst_ni) begin
@@ -434,7 +435,7 @@ module controller
434435
hwstack_fifo_push = 1'b0;
435436
hwstack_pushing_o = 1'b0;
436437
gpr_we_o = 1'b0;
437-
gpr_waddr_o = 5'd2; // x2 = sp
438+
gpr_waddr_o = 5'd2; // x2 = sp
438439
gpr_wdata_o = kernel_stack_pointer_i;
439440
unique case (hwstack_fill_state_q)
440441

@@ -495,7 +496,7 @@ module controller
495496
HWSTACK_DRAIN_IDLE: begin
496497
if (ex_valid_i && clic_irq_i && (|clic_rstk_i)) begin
497498
hwstack_drain_address_d = (clic_rstk_i == 2'b01) ? trap_frame_base_i : task_context_base_i;
498-
hwstack_drain_state_d = HWSTACK_DRAIN_SEND_REQ;
499+
hwstack_drain_state_d = HWSTACK_DRAIN_SEND_REQ;
499500
end
500501
end
501502

@@ -508,7 +509,7 @@ module controller
508509
hwstack_dcache_req_valid = 1'b1;
509510
if (dcache_rsp_i.data_gnt) begin
510511
hwstack_fifo_pop = 1'b1;
511-
hwstack_drain_address_d = hwstack_drain_address_q + (CVA6Cfg.XLEN/8);
512+
hwstack_drain_address_d = hwstack_drain_address_q + (CVA6Cfg.XLEN / 8);
512513
hwstack_drain_state_d = HWSTACK_DRAIN_SEND_REQ;
513514
end else begin
514515
hwstack_drain_state_d = HWSTACK_DRAIN_WAIT_GNT;
@@ -520,7 +521,7 @@ module controller
520521
hwstack_dcache_req_valid = 1'b1;
521522
if (dcache_rsp_i.data_gnt) begin
522523
hwstack_fifo_pop = 1'b1;
523-
hwstack_drain_address_d = hwstack_drain_address_q + (CVA6Cfg.XLEN/8);
524+
hwstack_drain_address_d = hwstack_drain_address_q + (CVA6Cfg.XLEN / 8);
524525
hwstack_drain_state_d = HWSTACK_DRAIN_SEND_REQ;
525526
end
526527
end

‎core/csr_regfile.sv‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -612,8 +612,7 @@ module csr_regfile
612612
if (CVA6Cfg.RVXHCLIC)
613613
csr_rdata = clic_mode_o ? {vstvt_q, 8'b0} : '0; // vstvt reads 0 in CLINT mode
614614
else read_access_exception = 1'b1;
615-
riscv::CSR_VSTFA_INC,
616-
riscv::CSR_VSTFA:
615+
riscv::CSR_VSTFA_INC, riscv::CSR_VSTFA:
617616
if (CVA6Cfg.RVH) csr_rdata = vstfa_q;
618617
else read_access_exception = 1'b1;
619618
riscv::CSR_VSTCA:
@@ -692,8 +691,7 @@ module csr_regfile
692691
read_access_exception = 1'b1;
693692
end
694693
end
695-
riscv::CSR_STFA_INC,
696-
riscv::CSR_STFA: begin
694+
riscv::CSR_STFA_INC, riscv::CSR_STFA: begin
697695
if (CVA6Cfg.RVS) begin
698696
csr_rdata = stfa_q;
699697
end else begin
@@ -2471,8 +2469,10 @@ module csr_regfile
24712469
end
24722470
end
24732471

2474-
riscv::CSR_DCACHE, riscv::CSR_DCACHE_SMODE: dcache_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit
2475-
riscv::CSR_ICACHE, riscv::CSR_ICACHE_SMODE: icache_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit
2472+
riscv::CSR_DCACHE, riscv::CSR_DCACHE_SMODE:
2473+
dcache_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit
2474+
riscv::CSR_ICACHE, riscv::CSR_ICACHE_SMODE:
2475+
icache_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit
24762476
riscv::CSR_FENCE_T_PAD: fence_t_pad_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]};
24772477
riscv::CSR_FENCE_T_SEL: fence_t_sel_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]};
24782478
riscv::CSR_FENCE_T_CEIL: fence_t_ceil_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]};

‎core/cva6.sv‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -370,7 +370,7 @@ module cva6
370370
input logic [$clog2(CVA6Cfg.CLICNumInterruptSrc)-1:0] clic_irq_id_i, // interrupt source ID
371371
input logic [7:0] clic_irq_level_i, // interrupt level is 8-bit from CLIC spec
372372
input riscv::priv_lvl_t clic_irq_priv_i, // CLIC interrupt privilege level
373-
input logic [1:0] clic_irq_rstk_i, // CLIC interrupt register stacking configuration
373+
input logic [1:0] clic_irq_rstk_i, // CLIC interrupt register stacking configuration
374374
input logic clic_irq_v_i, // CLIC interrupt virtualization bit (only for vCLIC)
375375
input logic [5:0] clic_irq_vsid_i, // CLIC interrupt Virtual Supervisor ID (only for vCLIC)
376376
input logic clic_irq_shv_i, // selective hardware vectoring bit
@@ -720,8 +720,8 @@ module cva6
720720
logic [CVA6Cfg.VLEN-1:0] trap_frame_base;
721721
logic [CVA6Cfg.VLEN-1:0] task_context_base;
722722
logic [CVA6Cfg.XLEN-1:0] kernel_stack_pointer;
723-
logic [31:0] [CVA6Cfg.XLEN-1:0] int_regs;
724-
logic [31:0] [CVA6Cfg.XLEN-1:0] fp_regs;
723+
logic [31:0][CVA6Cfg.XLEN-1:0] int_regs;
724+
logic [31:0][CVA6Cfg.XLEN-1:0] fp_regs;
725725
logic [11:0] load_page_offset;
726726
logic load_page_offset_matches;
727727
logic hwstack_pushing;
@@ -1614,7 +1614,7 @@ module cva6
16141614
end
16151615
assign dcache_req_ports_cache_ex[1] = dcache_req_from_cache[1];
16161616
assign dcache_req_ports_cache_acc[0] = '0;
1617-
assign dcache_req_ports_cache_ctrl = dcache_req_from_cache[2];
1617+
assign dcache_req_ports_cache_ctrl = dcache_req_from_cache[2];
16181618
always_comb begin : gen_dcache_req_store_data_gnt
16191619
dcache_req_ports_cache_ex[2] = dcache_req_from_cache[3];
16201620
dcache_req_ports_cache_acc[1] = dcache_req_from_cache[3];

‎core/ex_stage.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -248,7 +248,7 @@ module ex_stage
248248
// Page offset for address aliasing checks - CONTROLLER
249249
output logic [11:0] page_offset_o,
250250
// Page offset matches - CONTROLLER
251-
input logic page_offset_matches_i,
251+
input logic page_offset_matches_i,
252252
// Report the PMP configuration - CSR_REGFILE
253253
input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i,
254254
// Report the PMP addresses - CSR_REGFILE

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