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test: improve testbench
1 parent 223fbde commit 8fe6970

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Lines changed: 344 additions & 3 deletions

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‎Bender.yml‎

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Original file line numberDiff line numberDiff line change
@@ -307,6 +307,7 @@ sources:
307307
- test/hw/cva6tb_pkg.sv
308308
- test/hw/bootrom/cva6tb_bootrom.sv
309309
- test/hw/cva6tb_clk_rst_gen.sv
310+
- test/hw/cva6tb_hwmon.sv
310311
- test/hw/cva6tb_regs.sv
311312
- test/hw/cva6tb_rtc_timer.sv
312313
- test/hw/cva6tb_sim_console.sv

‎test/hw/cva6tb_hwmon.sv‎

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package cva6tb_hwmon_pkg;
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// Internal address width; 5 bits covers offsets 0x00–0x10.
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localparam int unsigned IntAddrWidth = 5;
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// Register map (write-only):
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// RELEASE 0x00 wdata = task_id → record release cycle, reset per-task state,
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// compute deadline = time_i + period_q[task_id]
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// PERIOD_LO 0x04 wdata[31:0] → stage low 32 bits of task period (init only)
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// PERIOD_HI 0x08 wdata[31:0] → commit {HI,LO} as period for last RELEASE'd task
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// START 0x0C wdata = task_id → open measurement window; handles preemption
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// STOP 0x10 wdata = task_id → close window, flush CSV row
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localparam logic [IntAddrWidth-1:0] CVA6TB_HWMON_RELEASE_OFFSET = 5'h00;
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localparam logic [IntAddrWidth-1:0] CVA6TB_HWMON_PERIOD_LO_OFFSET = 5'h04;
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localparam logic [IntAddrWidth-1:0] CVA6TB_HWMON_PERIOD_HI_OFFSET = 5'h08;
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localparam logic [IntAddrWidth-1:0] CVA6TB_HWMON_START_OFFSET = 5'h0C;
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localparam logic [IntAddrWidth-1:0] CVA6TB_HWMON_STOP_OFFSET = 5'h10;
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localparam int unsigned NumTasks = 32;
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localparam int unsigned TaskIdWidth = $clog2(NumTasks);
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typedef logic [TaskIdWidth-1:0] task_id_t;
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function automatic void mon_log(string msg);
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$display("@%t | [MON] %s", $realtime, msg);
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endfunction
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endpackage
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module cva6tb_hwmon
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#(
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parameter type reg_req_t = logic,
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parameter type reg_rsp_t = logic
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) (
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input logic clk_i,
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input logic rst_ni,
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input reg_req_t reg_req_i,
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output reg_rsp_t reg_rsp_o,
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input logic [63:0] time_i,
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// Single-cycle event pulses tapped directly from CVA6 RTL.
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// Each signal is high for exactly one cycle per miss event.
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input logic l1_icache_miss_i,
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input logic l1_dcache_miss_i,
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input logic itlb_miss_i,
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input logic dtlb_miss_i
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);
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import cva6tb_hwmon_pkg::*;
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// Write-only peripheral: always ready, never errors, no read data.
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assign reg_rsp_o.ready = 1'b1;
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assign reg_rsp_o.error = 1'b0;
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assign reg_rsp_o.rdata = '0;
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// ---------------------------------------------------------------------------
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// Decode incoming bus transaction
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// ---------------------------------------------------------------------------
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logic req_write;
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logic [IntAddrWidth-1:0] req_addr;
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task_id_t req_task_id;
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logic [31:0] req_wdata32;
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assign req_write = reg_req_i.valid & reg_req_i.write;
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assign req_addr = reg_req_i.addr[IntAddrWidth-1:0];
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assign req_task_id = task_id_t'(reg_req_i.wdata);
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assign req_wdata32 = reg_req_i.wdata[31:0];
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// ---------------------------------------------------------------------------
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// Internal state
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// ---------------------------------------------------------------------------
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// Free-running cycle counter.
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logic [63:0] cycle_q;
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// Per-task accumulated state (indexed by task_id).
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logic [63:0] release_cycle_q [NumTasks]; // cycle at last RELEASE
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logic [63:0] deadline_q [NumTasks]; // absolute deadline for current job
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logic [63:0] first_start_cycle_q[NumTasks]; // cycle of first CPU grant this job
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logic first_start_pend_q [NumTasks]; // 1 = first CPU grant not yet seen
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logic [63:0] exec_time_q [NumTasks]; // accumulated CPU time (across preemptions)
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logic [63:0] icache_count_q [NumTasks]; // miss pulses since last RELEASE
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logic [63:0] dcache_count_q [NumTasks];
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logic [63:0] itlb_count_q [NumTasks];
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logic [63:0] dtlb_count_q [NumTasks];
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logic [31:0] preempt_count_q [NumTasks]; // preemptions this job
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// Active window state.
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logic active_q; // measurement window is open
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task_id_t current_task_q; // task currently on CPU
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logic [63:0] window_start_q; // cycle_q at last START write
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// Per-task period (written once at init via PERIOD_LO/HI).
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logic [63:0] period_q [NumTasks];
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// PERIOD staging: two-phase write for 64-bit period over 32-bit bus.
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logic [31:0] period_lo_q;
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task_id_t deadline_target_q; // task whose period is being staged
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// ---------------------------------------------------------------------------
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// Free-running cycle counter
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// ---------------------------------------------------------------------------
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) cycle_q <= '0;
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else cycle_q <= cycle_q + 1;
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end
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// ---------------------------------------------------------------------------
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// Per-task state machine
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//
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// RELEASE write : resets all per-task accumulators for the released task.
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// START write : opens a CPU window. If another task was active (preemption),
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// the outgoing task's partial exec time is committed first.
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// STOP write : finalises the CPU window; total exec_time is committed so the
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// logging block can read the correct final value.
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// Active cycles : miss pulses accumulated for current_task_q.
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//
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// Misses on the START and STOP write cycles are excluded (scheduler/ecall
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// overhead) because req_write suppresses the else-if accumulation branch.
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// ---------------------------------------------------------------------------
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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active_q <= 1'b0;
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current_task_q <= '0;
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window_start_q <= '0;
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period_lo_q <= '0;
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deadline_target_q <= '0;
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for (int i = 0; i < NumTasks; i++) begin
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release_cycle_q[i] <= '0;
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deadline_q[i] <= '0;
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period_q[i] <= '0;
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first_start_cycle_q[i] <= '0;
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first_start_pend_q[i] <= 1'b0;
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exec_time_q[i] <= '0;
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icache_count_q[i] <= '0;
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dcache_count_q[i] <= '0;
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itlb_count_q[i] <= '0;
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dtlb_count_q[i] <= '0;
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preempt_count_q[i] <= '0;
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end
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end else if (req_write) begin
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case (req_addr)
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// --- New job released: reset all per-task accumulators,
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// deadline auto-computed from stored period ---
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CVA6TB_HWMON_RELEASE_OFFSET: begin
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release_cycle_q[req_task_id] <= cycle_q;
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deadline_q[req_task_id] <= time_i + period_q[req_task_id];
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first_start_pend_q[req_task_id] <= 1'b1;
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exec_time_q[req_task_id] <= '0;
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icache_count_q[req_task_id] <= '0;
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dcache_count_q[req_task_id] <= '0;
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itlb_count_q[req_task_id] <= '0;
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dtlb_count_q[req_task_id] <= '0;
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preempt_count_q[req_task_id] <= '0;
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deadline_target_q <= req_task_id;
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end
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// --- Stage low 32 bits of 64-bit period (init only) ---
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CVA6TB_HWMON_PERIOD_LO_OFFSET: begin
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period_lo_q <= req_wdata32;
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end
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// --- Commit full 64-bit period for the task from the last RELEASE ---
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CVA6TB_HWMON_PERIOD_HI_OFFSET: begin
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period_q[deadline_target_q] <= {req_wdata32, period_lo_q};
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end
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// --- Open measurement window; handle preemption transparently ---
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CVA6TB_HWMON_START_OFFSET: begin
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if (active_q && (current_task_q != req_task_id)) begin
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// Preemption: commit partial exec time for the task being kicked off.
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exec_time_q[current_task_q] <=
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exec_time_q[current_task_q] + (cycle_q - window_start_q);
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preempt_count_q[current_task_q] <= preempt_count_q[current_task_q] + 1;
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end
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active_q <= 1'b1;
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current_task_q <= req_task_id;
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window_start_q <= cycle_q;
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// Record the very first CPU grant this job (used for sched_jitter).
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if (first_start_pend_q[req_task_id]) begin
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first_start_cycle_q[req_task_id] <= cycle_q;
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first_start_pend_q[req_task_id] <= 1'b0;
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end
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end
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// --- Close measurement window ---
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CVA6TB_HWMON_STOP_OFFSET: begin
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if (active_q) begin
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exec_time_q[current_task_q] <=
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exec_time_q[current_task_q] + (cycle_q - window_start_q);
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active_q <= 1'b0;
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end
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end
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default: ;
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endcase
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end else if (active_q) begin
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// Accumulate miss pulses for the task currently on CPU.
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icache_count_q[current_task_q] <=
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icache_count_q[current_task_q] + 64'(l1_icache_miss_i);
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dcache_count_q[current_task_q] <=
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dcache_count_q[current_task_q] + 64'(l1_dcache_miss_i);
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itlb_count_q[current_task_q] <=
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itlb_count_q[current_task_q] + 64'(itlb_miss_i);
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dtlb_count_q[current_task_q] <=
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dtlb_count_q[current_task_q] + 64'(dtlb_miss_i);
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end
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end
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// ---------------------------------------------------------------------------
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// Combinational signals for CSV logging
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//
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// These are evaluated in the active region using pre-NBA _q values,
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// which are the fully accumulated totals before the STOP update fires.
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// exec_cycles manually adds the current window so the log sees the final total.
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// ---------------------------------------------------------------------------
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logic [63:0] log_exec_cycles;
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logic [63:0] log_response_time;
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logic [63:0] log_sched_jitter;
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logic log_deadline_miss;
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assign log_exec_cycles = exec_time_q[current_task_q] + (cycle_q - window_start_q);
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assign log_response_time = cycle_q - release_cycle_q[current_task_q];
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assign log_sched_jitter = first_start_cycle_q[current_task_q] -
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release_cycle_q[current_task_q];
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assign log_deadline_miss = (time_i > deadline_q[current_task_q]) ? 1'b1 : 1'b0;
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// ---------------------------------------------------------------------------
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// CSV logging
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//
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// Runs in the active region of the STOP posedge. Because the always_ff above
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// uses non-blocking assignments, all _q values (and the combinational signals
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// derived from them) reflect the pre-update totals — the correct final values
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// for the completed job.
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//
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// Columns:
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// task_id : task identifier
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// exec_cycles : total CPU time (excluding scheduler and ecall cycles)
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// response_time : STOP cycle − RELEASE cycle
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// sched_jitter : first START cycle − RELEASE cycle
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// deadline_miss : 1 if time_i at STOP > absolute deadline (in time_i ticks)
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// preemptions : number of times the task was preempted this job
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// icache_misses : I-cache miss pulses attributed to this task
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// dcache_misses : D-cache miss pulses
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// itlb_misses : ITLB miss pulses
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// dtlb_misses : DTLB miss pulses
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// ---------------------------------------------------------------------------
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localparam string FileName = "hwmon_log.csv";
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integer log_file;
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function automatic void setup();
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log_file = $fopen(FileName, "w");
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if (log_file == 0) begin
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$display("ERROR: Could not open log file %s", FileName);
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$finish;
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end
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$fwrite(log_file, "task_id,exec_cycles,response_time,sched_jitter,deadline_miss,preemptions,icache_misses,dcache_misses,itlb_misses,dtlb_misses\n");
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endfunction
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function automatic void cleanup();
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$fclose(log_file);
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endfunction
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initial setup();
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always @(posedge clk_i) begin
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if (req_write) begin
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case (req_addr)
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CVA6TB_HWMON_RELEASE_OFFSET:
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mon_log($sformatf("RELEASE task %0d @time=%0d, deadline=%0d",
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req_task_id, time_i, time_i + period_q[req_task_id]));
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CVA6TB_HWMON_START_OFFSET: begin
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if (active_q && current_task_q != req_task_id)
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mon_log($sformatf("START task %0d @time=%0d (preempts task=%0d)",
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req_task_id, time_i, current_task_q));
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else
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mon_log($sformatf("START task %0d @time=%0d",
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req_task_id, time_i));
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end
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CVA6TB_HWMON_STOP_OFFSET: begin
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if (active_q)
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mon_log($sformatf("STOP task %0d @time=%0d, %s",
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current_task_q, time_i, log_deadline_miss ? "MISS" : "ok"));
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end
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default: ;
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endcase
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end
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if (req_write && req_addr == CVA6TB_HWMON_STOP_OFFSET && active_q) begin
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$fwrite(log_file, "%0d,%0d,%0d,%0d,%0d,%0d,%0d,%0d,%0d,%0d\n",
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current_task_q,
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log_exec_cycles,
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log_response_time,
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log_sched_jitter,
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log_deadline_miss,
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preempt_count_q[current_task_q],
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icache_count_q[current_task_q],
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dcache_count_q[current_task_q],
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itlb_count_q[current_task_q],
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dtlb_count_q[current_task_q]);
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$fflush(log_file);
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end
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end
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final cleanup();
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endmodule

‎test/hw/cva6tb_pkg.sv‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -40,16 +40,17 @@ package cva6tb_pkg;
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localparam int unsigned AxiSlvIdDram = 2;
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localparam int unsigned AxiSlvIdSpm = 3;
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43-
localparam int unsigned RegbusOutNum = 8;
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localparam int unsigned RegbusRulesNum = 8;
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localparam int unsigned RegbusOutNum = 9;
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localparam int unsigned RegbusRulesNum = 9;
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localparam int unsigned RegbusErrId = 0;
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localparam int unsigned RegbusBootromId = 1;
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localparam int unsigned RegbusClintId = 2;
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localparam int unsigned RegbusPlicId = 3;
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localparam int unsigned RegbusPCRsId = 4;
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localparam int unsigned RegbusConsoleId = 5;
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localparam int unsigned RegbusRTCTimerId = 6;
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localparam int unsigned RegbusClicId = 7;
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localparam int unsigned RegbusHwmonId = 7;
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localparam int unsigned RegbusClicId = 8;
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localparam int unsigned NumClicIntIrqs = 18;
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localparam int unsigned NumClicExtIrqs = 256 - NumClicIntIrqs;
@@ -164,6 +165,9 @@ package cva6tb_pkg;
164165
// RTC timer region
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localparam reg_addr_t RTCTimerBaseAddr = 32'h1000_2000;
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localparam reg_addr_t RTCTimerSize = 32'h0000_1000;
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// HWMon region
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localparam reg_addr_t HwmonBaseAddr = 32'h1000_3000;
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localparam reg_addr_t HwmonSize = 32'h0000_1000;
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// CLIC region
168172
localparam reg_addr_t ClicBaseAddr = 32'h1004_0000;
169173
localparam reg_addr_t ClicSize = 32'h0003_0000;
@@ -184,6 +188,7 @@ package cva6tb_pkg;
184188
reg_addr_rule_t'{ idx: RegbusPCRsId, start_addr: PCRsBaseAddr, end_addr: (PCRsBaseAddr + PCRsSize) }, // Platform Control Registers
185189
reg_addr_rule_t'{ idx: RegbusConsoleId, start_addr: ConsoleBaseAddr, end_addr: (ConsoleBaseAddr + ConsoleSize) }, // Sim console
186190
reg_addr_rule_t'{ idx: RegbusRTCTimerId, start_addr: RTCTimerBaseAddr, end_addr: (RTCTimerBaseAddr + RTCTimerSize) }, // RTC timer
191+
reg_addr_rule_t'{ idx: RegbusHwmonId, start_addr: HwmonBaseAddr, end_addr: (HwmonBaseAddr + HwmonSize) }, // HWMonitor unit
187192
reg_addr_rule_t'{ idx: RegbusClicId, start_addr: ClicBaseAddr, end_addr: (ClicBaseAddr + ClicSize) } // CLIC
188193
};
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