Add hybrid cache / spm support to dcache

Co-authored-by: Christopher Reinwardt <creinwar@iis.ee.ethz.ch>

Author: ezelioli

Bender.yml

@@ -180,6 +180,7 @@ sources:
       - core/cache_subsystem/wt_cache_subsystem.sv
       - core/cache_subsystem/wt_axi_adapter.sv
       - core/cache_subsystem/ispm_ctrl.sv
+      - core/cache_subsystem/dspm_ctrl.sv
       - core/cache_subsystem/cva6_icache.sv
       - core/cache_subsystem/tag_cmp.sv
       - core/cache_subsystem/cache_ctrl.sv

core/cache_subsystem/dspm_ctrl.sv

@@ -0,0 +1,173 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+//
+// Author: Christopher Reinwardt <creinwar@student.ethz.ch>
+// --------------
+// D-Cache SPM controller
+// --------------
+//
+// Description: Arbitrates access to data cache memories in SPM mode
+// Requests from lower index input ports are prioritized
+//
+
+`include "common_cells/registers.svh"
+
+module dspm_ctrl
+  import std_cache_pkg::*;
+  import ariane_pkg::*;
+#(
+    parameter  type         dcache_req_i_t = logic,
+    parameter  type         dcache_req_o_t = logic,
+    parameter  int unsigned NR_PORTS       = 3,
+    parameter  int unsigned NR_WAYS        = 4,
+    parameter  int unsigned LINE_WIDTH     = 128,
+    parameter  int unsigned ADDR_WIDTH     = 64,
+    parameter  int unsigned MEMORY_WIDTH   = 172,
+    parameter  int unsigned IDX_WIDTH      = 12,                     // Cache index + byte offset
+    parameter  int unsigned NR_WAIT_STAGES = 1,
+    // Derived parameters, DO NOT OVERRIDE
+    localparam int unsigned BE_WIDTH       = (MEMORY_WIDTH + 7) / 8
+) (
+    input logic clk_i,
+    input logic rst_ni,
+
+    input logic [NR_WAYS-1:0] active_ways_i,
+
+    // Request ports
+    input  dcache_req_i_t [NR_PORTS-1:0] spm_req_ports_i,
+    output dcache_req_o_t [NR_PORTS-1:0] spm_req_ports_o,
+
+    output logic [     NR_WAYS-1:0]                   req_o,
+    output logic [  ADDR_WIDTH-1:0]                   addr_o,
+    output logic [MEMORY_WIDTH-1:0]                   wdata_o,
+    output logic                                      we_o,
+    output logic [    BE_WIDTH-1:0]                   be_o,
+    input  logic [     NR_WAYS-1:0][MEMORY_WIDTH-1:0] rdata_i
+);
+
+  localparam WAY_INDEX_BITS = $clog2(NR_WAYS);
+  logic [WAY_INDEX_BITS-1:0] way_idx, way_idx_d, way_idx_q;
+
+  // One hot encoded
+  logic [$clog2(NR_PORTS)-1:0] portsel, portsel_d, portsel_q;
+
+  // SRAM latency counter
+  logic [$clog2(NR_WAIT_STAGES)-1:0] wait_stage_d, wait_stage_q;
+
+  // Helper variable to assemble the full cache-line from parts
+  logic [LINE_WIDTH-1:0] write_line;
+
+  // Word offset within the cacheline
+  logic [$clog2(LINE_WIDTH/8)-$clog2(riscv::XLEN/8)-1:0] cl_offset, cl_offset_d, cl_offset_q;
+
+  // Port selection logic
+  always_comb begin
+    portsel = '{default: 0};
+
+    for (int unsigned i = 0; i < NR_PORTS; i++) begin
+      // This data request is only coming from the actual requester
+      // if it is a write
+      // Otherwise this is coming from the request splitter
+      // => Only grant if it is a write
+      if (spm_req_ports_i[i].data_req) begin
+        portsel = i;
+        break;
+      end
+    end
+  end
+
+  // Static assignments
+  // This saves which cache way this address targets
+  assign way_idx = spm_req_ports_i[portsel].address_tag[0+:WAY_INDEX_BITS];
+
+  // This saves at which offset within a cacheline we are
+  assign cl_offset = spm_req_ports_i[portsel].address_index[$clog2(
+      LINE_WIDTH/8
+  )-1:$clog2(
+      riscv::XLEN/8
+  )];
+
+  assign addr_o = spm_req_ports_i[portsel].address_index;
+  // This zeros the tag and other status bits,
+  // while writing the payload to the SRAM
+  assign wdata_o = {{(MEMORY_WIDTH - LINE_WIDTH) {1'b0}}, write_line};
+  assign we_o = spm_req_ports_i[portsel].data_we;
+
+  always_comb begin
+    cl_offset_d                                        = cl_offset_q;
+    portsel_d                                          = portsel_q;
+    wait_stage_d                                       = wait_stage_q;
+    way_idx_d                                          = way_idx_q;
+
+    spm_req_ports_o                                    = '{default: 0};
+
+    write_line                                         = '{default: 0};
+    // We assemble the write data unconditionally as the
+    // write is controlled by the write enable
+    write_line[(cl_offset*riscv::XLEN)+:riscv::XLEN]   = spm_req_ports_i[portsel].data_wdata;
+
+    req_o                                              = '{default: 0};
+
+    // By default we'll always write the tag (so that it's zeroed)
+    be_o                                               = '{default: 0};
+    be_o[BE_WIDTH-1:(LINE_WIDTH/8)]                    = '{default: 1'b1};
+    // Only enable the part of the cacheline that we actually want to update
+    be_o[(cl_offset*(riscv::XLEN/8))+:(riscv::XLEN/8)] = spm_req_ports_i[portsel].data_be;
+
+    // Decrease the wait counter if it's not already 0
+    if (wait_stage_q) wait_stage_d = wait_stage_q - ($clog2(NR_WAIT_STAGES) + 1)'(1);
+
+    // Accept a new request if one is pending and we're not waiting for
+    // the SRAM anymore
+    if (spm_req_ports_i[portsel].data_req && wait_stage_q == '0) begin
+      portsel_d = portsel;
+      way_idx_d = way_idx;
+      // Record the offset
+      cl_offset_d = cl_offset;
+
+      // Reset the counter on every new request
+      wait_stage_d = NR_WAIT_STAGES;
+
+      // Are we allowed to use this memory?
+      if (active_ways_i[way_idx]) begin
+        req_o[way_idx] = 1'b1;
+
+        // Otherwise just respond with badcable
+      end else begin
+        spm_req_ports_o[portsel].data_rdata = 64'hCA11AB1E_BADCAB1E;
+        spm_req_ports_o[portsel].data_gnt = spm_req_ports_i[portsel].data_we;
+        spm_req_ports_o[portsel].data_rvalid = ~spm_req_ports_i[portsel].data_we;
+
+        // We don't need to wait for the memory here, as we did not access any
+        wait_stage_d = '0;
+      end
+    end
+
+    // Later acknowledge => Use the registered version of the select signals
+    if (wait_stage_q == 32'b1) begin
+      spm_req_ports_o[portsel_q].data_gnt = spm_req_ports_i[portsel_q].data_we;
+      spm_req_ports_o[portsel_q].data_rvalid = ~spm_req_ports_i[portsel_q].data_we;
+      spm_req_ports_o[portsel_q].data_rdata = rdata_i[way_idx_q][(cl_offset_q * riscv::XLEN) +: riscv::XLEN];
+
+      // Same cycle acknowledge => Use the unregistered version
+    end else if (NR_WAIT_STAGES == 0) begin
+
+      spm_req_ports_o[portsel].data_gnt = spm_req_ports_i[portsel].data_we;
+      spm_req_ports_o[portsel].data_rvalid = ~spm_req_ports_i[portsel].data_we;
+      spm_req_ports_o[portsel].data_rdata = rdata_i[way_idx][(cl_offset*riscv::XLEN)+:riscv::XLEN];
+    end
+  end
+
+  `FF(cl_offset_q, cl_offset_d, '0, clk_i, rst_ni)
+  `FF(wait_stage_q, wait_stage_d, '0, clk_i, rst_ni)
+  `FF(way_idx_q, way_idx_d, '0, clk_i, rst_ni)
+  `FF(portsel_q, portsel_d, '0, clk_i, rst_ni)
+
+endmodule

core/cache_subsystem/miss_handler.sv

@@ -35,6 +35,7 @@ module miss_handler
     output logic miss_o,
     input logic busy_i,  // dcache is busy with something
     input logic init_ni,  // do not init after reset
+    input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] spm_ways_i,  // the mask of cache ways currently owned by the SPM
     // Bypass or miss
     input logic [NR_PORTS-1:0][$bits(miss_req_t)-1:0] miss_req_i,
     // Bypass handling
@@ -177,8 +178,8 @@ module miss_handler
     automatic logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] evict_way, valid_way;
 
     for (int unsigned i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) begin
-      evict_way[i] = data_i[i].valid & (|data_i[i].dirty);
-      valid_way[i] = data_i[i].valid;
+      evict_way[i] = data_i[i].valid & (|data_i[i].dirty) & ~spm_ways_i[i];
+      valid_way[i] = data_i[i].valid | spm_ways_i[i];
     end
     // ----------------------
     // Default Assignments
@@ -681,15 +682,37 @@ module miss_handler
   // -----------------
   // Replacement LFSR
   // -----------------
+
+  logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] lfsr_oh_raw, cache_ways_oh;
+  logic [$clog2(CVA6Cfg.DCACHE_SET_ASSOC)-1:0] lfsr_bin_raw, cache_ways_bin;
+
   lfsr_8bit #(
       .WIDTH(CVA6Cfg.DCACHE_SET_ASSOC)
   ) i_lfsr (
       .en_i          (lfsr_enable),
-      .refill_way_oh (lfsr_oh),
-      .refill_way_bin(lfsr_bin),
+      .refill_way_oh (lfsr_oh_raw),
+      .refill_way_bin(lfsr_bin_raw),
       .*
   );
 
+  // Calculate the first cache owned way
+  assign cache_ways_oh = (spm_ways_i + 1'b1) & ~spm_ways_i;
+
+  // And the binary representation of it
+  always_comb begin
+    cache_ways_bin = 0;
+    for (int unsigned i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) begin
+      if (cache_ways_oh[i]) begin
+        cache_ways_bin = i;
+      end
+    end
+  end
+
+  // If the LFSR chose a cache owned way we can use that one
+  // otherwise use the first cache owned way
+  assign lfsr_oh  = (lfsr_oh_raw & ~spm_ways_i) ? lfsr_oh_raw : cache_ways_oh;
+  assign lfsr_bin = (lfsr_oh_raw & ~spm_ways_i) ? lfsr_bin_raw : cache_ways_bin;
+
   // -----------------
   // Struct Split
   // -----------------

core/cache_subsystem/std_cache_subsystem.sv

@@ -61,6 +61,7 @@ module std_cache_subsystem
     input logic dcache_flush_i,  // high until acknowledged
     output logic                           dcache_flush_ack_o,     // send a single cycle acknowledge signal when the cache is flushed
     output logic dcache_miss_o,  // we missed on a ld/st
+    input [CVA6Cfg.DCACHE_SET_ASSOC-1:0]   dcache_spm_ways_i,      // dcache ways configured as SPM
     output logic                           wbuffer_empty_o,        // statically set to 1, as there is no wbuffer in this cache system
     // Request ports
     input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i,  // to/from LSU
@@ -142,6 +143,7 @@ module std_cache_subsystem
       .busy_o      (dcache_busy),
       .stall_i     (stall_i),
       .init_ni     (init_ni),
+      .dcache_spm_ways_i(dcache_spm_ways_i),
       .axi_bypass_o(axi_req_bypass),
       .axi_bypass_i(axi_resp_bypass),
       .axi_data_o  (axi_req_data),