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ezelioliezelioli
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Hybrid cache/spm: linting
1 parent a5ca851 commit ed87ca9

7 files changed

Lines changed: 166 additions & 166 deletions

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‎core/cache_subsystem/cva6_hpdcache_subsystem.sv‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -157,26 +157,26 @@ module cva6_hpdcache_subsystem
157157
.icache_rtrn_t(icache_rtrn_t),
158158
.RdTxId(ICACHE_RDTXID)
159159
) i_cva6_icache (
160-
.clk_i (clk_i),
161-
.rst_ni (rst_ni),
162-
.flush_i (icache_flush_i),
163-
.en_i (icache_en_i),
164-
.miss_o (icache_miss_o),
165-
.busy_o (),
166-
.stall_i (1'b0),
167-
.init_ni (1'b0),
160+
.clk_i (clk_i),
161+
.rst_ni (rst_ni),
162+
.flush_i (icache_flush_i),
163+
.en_i (icache_en_i),
164+
.miss_o (icache_miss_o),
165+
.busy_o (),
166+
.stall_i (1'b0),
167+
.init_ni (1'b0),
168168
.icache_spm_ways_i('0),
169-
.areq_i (icache_areq_i),
170-
.areq_o (icache_areq_o),
171-
.dreq_i (icache_dreq_i),
172-
.dreq_o (icache_dreq_o),
173-
.ispm_req_i ('0),
174-
.ispm_req_o (),
175-
.mem_rtrn_vld_i(icache_miss_resp_valid),
176-
.mem_rtrn_i (icache_miss_resp),
177-
.mem_data_req_o(icache_miss_valid),
178-
.mem_data_ack_i(icache_miss_ready),
179-
.mem_data_o (icache_miss)
169+
.areq_i (icache_areq_i),
170+
.areq_o (icache_areq_o),
171+
.dreq_i (icache_dreq_i),
172+
.dreq_o (icache_dreq_o),
173+
.ispm_req_i ('0),
174+
.ispm_req_o (),
175+
.mem_rtrn_vld_i (icache_miss_resp_valid),
176+
.mem_rtrn_i (icache_miss_resp),
177+
.mem_data_req_o (icache_miss_valid),
178+
.mem_data_ack_i (icache_miss_ready),
179+
.mem_data_o (icache_miss)
180180
);
181181
// }}}
182182

‎core/cache_subsystem/cva6_icache.sv‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -45,29 +45,29 @@ module cva6_icache
4545
input logic rst_ni,
4646

4747
/// flush the icache, flush and kill have to be asserted together
48-
input logic flush_i,
48+
input logic flush_i,
4949
/// enable icache
50-
input logic en_i,
50+
input logic en_i,
5151
/// to performance counter
52-
output logic miss_o,
53-
output logic busy_o,
54-
input logic stall_i,
55-
input logic init_ni, // do not init after enabling
56-
input logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0] icache_spm_ways_i,
52+
output logic miss_o,
53+
output logic busy_o,
54+
input logic stall_i,
55+
input logic init_ni, // do not init after enabling
56+
input logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0] icache_spm_ways_i,
5757
// address translation requests
58-
input icache_areq_t areq_i,
58+
input icache_areq_t areq_i,
5959
output icache_arsp_t areq_o,
6060
// data requests
61-
input icache_dreq_t dreq_i,
61+
input icache_dreq_t dreq_i,
6262
output icache_drsp_t dreq_o,
63-
input dcache_req_i_t ispm_req_i,
63+
input dcache_req_i_t ispm_req_i,
6464
output dcache_req_o_t ispm_req_o,
6565
// refill port
66-
input logic mem_rtrn_vld_i,
67-
input icache_rtrn_t mem_rtrn_i,
68-
output logic mem_data_req_o,
69-
input logic mem_data_ack_i,
70-
output icache_req_t mem_data_o
66+
input logic mem_rtrn_vld_i,
67+
input icache_rtrn_t mem_rtrn_i,
68+
output logic mem_data_req_o,
69+
input logic mem_data_ack_i,
70+
output icache_req_t mem_data_o
7171
);
7272

7373
localparam ICACHE_OFFSET_WIDTH = $clog2(CVA6Cfg.ICACHE_LINE_WIDTH / 8);
@@ -222,19 +222,19 @@ module cva6_icache
222222
logic cur_idx;
223223

224224
addr_decode #(
225-
.NoIndices ( 2 ),
226-
.NoRules ( 3 ),
227-
.addr_t ( paddr_t ),
228-
.rule_t ( rule_t )
225+
.NoIndices(2),
226+
.NoRules (3),
227+
.addr_t (paddr_t),
228+
.rule_t (rule_t)
229229
// .Napot ( 0 )
230230
) i_addr_dec (
231-
.addr_i ( areq_i.fetch_paddr ),
232-
.addr_map_i ( icache_spm_map ),
233-
.idx_o ( cur_idx ),
234-
.dec_valid_o ( ),
235-
.dec_error_o ( ),
236-
.en_default_idx_i ( 1'b1 ),
237-
.default_idx_i ( '0 )
231+
.addr_i (areq_i.fetch_paddr),
232+
.addr_map_i (icache_spm_map),
233+
.idx_o (cur_idx),
234+
.dec_valid_o (),
235+
.dec_error_o (),
236+
.en_default_idx_i(1'b1),
237+
.default_idx_i ('0)
238238
);
239239

240240
///////////////////////////////////////////////////////

‎core/cache_subsystem/cva6_icache_axi_wrapper.sv‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -126,26 +126,26 @@ module cva6_icache_axi_wrapper
126126
.icache_rtrn_t(icache_rtrn_t),
127127
.RdTxId(0)
128128
) i_cva6_icache (
129-
.clk_i (clk_i),
130-
.rst_ni (rst_ni),
131-
.flush_i (flush_i),
132-
.en_i (en_i),
133-
.miss_o (miss_o),
134-
.busy_o (busy_o),
135-
.stall_i (stall_i),
136-
.init_ni (init_ni),
129+
.clk_i (clk_i),
130+
.rst_ni (rst_ni),
131+
.flush_i (flush_i),
132+
.en_i (en_i),
133+
.miss_o (miss_o),
134+
.busy_o (busy_o),
135+
.stall_i (stall_i),
136+
.init_ni (init_ni),
137137
.icache_spm_ways_i(icache_spm_ways_i),
138-
.areq_i (areq_i),
139-
.areq_o (areq_o),
140-
.dreq_i (dreq_i),
141-
.dreq_o (dreq_o),
142-
.ispm_req_i (ispm_req_i),
143-
.ispm_req_o (ispm_req_o),
144-
.mem_rtrn_vld_i(icache_mem_rtrn_vld),
145-
.mem_rtrn_i (icache_mem_rtrn),
146-
.mem_data_req_o(icache_mem_data_req),
147-
.mem_data_ack_i(icache_mem_data_ack),
148-
.mem_data_o (icache_mem_data)
138+
.areq_i (areq_i),
139+
.areq_o (areq_o),
140+
.dreq_i (dreq_i),
141+
.dreq_o (dreq_o),
142+
.ispm_req_i (ispm_req_i),
143+
.ispm_req_o (ispm_req_o),
144+
.mem_rtrn_vld_i (icache_mem_rtrn_vld),
145+
.mem_rtrn_i (icache_mem_rtrn),
146+
.mem_data_req_o (icache_mem_data_req),
147+
.mem_data_ack_i (icache_mem_data_ack),
148+
.mem_data_o (icache_mem_data)
149149
);
150150

151151
// --------

‎core/cache_subsystem/std_cache_subsystem.sv‎

Lines changed: 42 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ module std_cache_subsystem
6161
input logic dcache_flush_i, // high until acknowledged
6262
output logic dcache_flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed
6363
output logic dcache_miss_o, // we missed on a ld/st
64-
input [CVA6Cfg.DCACHE_SET_ASSOC-1:0] dcache_spm_ways_i, // dcache ways configured as SPM
64+
input [CVA6Cfg.DCACHE_SET_ASSOC-1:0] dcache_spm_ways_i, // dcache ways configured as SPM
6565
output logic wbuffer_empty_o, // statically set to 1, as there is no wbuffer in this cache system
6666
// Request ports
6767
input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // to/from LSU
@@ -73,18 +73,18 @@ module std_cache_subsystem
7373

7474
assign wbuffer_empty_o = 1'b1;
7575

76-
axi_req_t axi_req_icache;
77-
axi_rsp_t axi_resp_icache;
78-
axi_req_t axi_req_bypass;
79-
axi_rsp_t axi_resp_bypass;
80-
axi_req_t axi_req_data;
81-
axi_rsp_t axi_resp_data;
76+
axi_req_t axi_req_icache;
77+
axi_rsp_t axi_resp_icache;
78+
axi_req_t axi_req_bypass;
79+
axi_rsp_t axi_resp_bypass;
80+
axi_req_t axi_req_data;
81+
axi_rsp_t axi_resp_data;
8282

8383
dcache_req_o_t d2i_cache_req_in;
8484
dcache_req_i_t d2i_cache_req_out;
8585

86-
logic icache_busy;
87-
logic dcache_busy;
86+
logic icache_busy;
87+
logic dcache_busy;
8888

8989
assign busy_o = icache_busy | dcache_busy;
9090

@@ -101,24 +101,24 @@ module std_cache_subsystem
101101
.axi_req_t(axi_req_t),
102102
.axi_rsp_t(axi_rsp_t)
103103
) i_cva6_icache_axi_wrapper (
104-
.clk_i (clk_i),
105-
.rst_ni (rst_ni),
106-
.priv_lvl_i(priv_lvl_i),
107-
.flush_i (icache_flush_i),
108-
.en_i (icache_en_i),
109-
.miss_o (icache_miss_o),
110-
.busy_o (icache_busy),
111-
.stall_i (stall_i),
112-
.init_ni (init_ni),
113-
.icache_spm_ways_i (icache_spm_ways_i),
114-
.areq_i (icache_areq_i),
115-
.areq_o (icache_areq_o),
116-
.dreq_i (icache_dreq_i),
117-
.dreq_o (icache_dreq_o),
118-
.ispm_req_i (d2i_cache_req_out),
119-
.ispm_req_o (d2i_cache_req_in),
120-
.axi_req_o (axi_req_icache),
121-
.axi_resp_i(axi_resp_icache)
104+
.clk_i (clk_i),
105+
.rst_ni (rst_ni),
106+
.priv_lvl_i (priv_lvl_i),
107+
.flush_i (icache_flush_i),
108+
.en_i (icache_en_i),
109+
.miss_o (icache_miss_o),
110+
.busy_o (icache_busy),
111+
.stall_i (stall_i),
112+
.init_ni (init_ni),
113+
.icache_spm_ways_i(icache_spm_ways_i),
114+
.areq_i (icache_areq_i),
115+
.areq_o (icache_areq_o),
116+
.dreq_i (icache_dreq_i),
117+
.dreq_o (icache_dreq_o),
118+
.ispm_req_i (d2i_cache_req_out),
119+
.ispm_req_o (d2i_cache_req_in),
120+
.axi_req_o (axi_req_icache),
121+
.axi_resp_i (axi_resp_icache)
122122
);
123123

124124
// decreasing priority
@@ -136,22 +136,22 @@ module std_cache_subsystem
136136
) i_nbdcache (
137137
.clk_i,
138138
.rst_ni,
139-
.enable_i (dcache_enable_i),
140-
.flush_i (dcache_flush_i),
141-
.flush_ack_o (dcache_flush_ack_o),
142-
.miss_o (dcache_miss_o),
143-
.busy_o (dcache_busy),
144-
.stall_i (stall_i),
145-
.init_ni (init_ni),
139+
.enable_i (dcache_enable_i),
140+
.flush_i (dcache_flush_i),
141+
.flush_ack_o (dcache_flush_ack_o),
142+
.miss_o (dcache_miss_o),
143+
.busy_o (dcache_busy),
144+
.stall_i (stall_i),
145+
.init_ni (init_ni),
146146
.dcache_spm_ways_i(dcache_spm_ways_i),
147-
.axi_bypass_o(axi_req_bypass),
148-
.axi_bypass_i(axi_resp_bypass),
149-
.axi_data_o (axi_req_data),
150-
.axi_data_i (axi_resp_data),
151-
.req_ports_i (dcache_req_ports_i),
152-
.req_ports_o (dcache_req_ports_o),
153-
.ispm_req_i (d2i_cache_req_in),
154-
.ispm_req_o (d2i_cache_req_out),
147+
.axi_bypass_o (axi_req_bypass),
148+
.axi_bypass_i (axi_resp_bypass),
149+
.axi_data_o (axi_req_data),
150+
.axi_data_i (axi_resp_data),
151+
.req_ports_i (dcache_req_ports_i),
152+
.req_ports_o (dcache_req_ports_o),
153+
.ispm_req_i (d2i_cache_req_in),
154+
.ispm_req_o (d2i_cache_req_out),
155155
.amo_req_i,
156156
.amo_resp_o
157157
);

‎core/cache_subsystem/std_nbdcache.sv‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -242,26 +242,26 @@ module std_nbdcache
242242
// Decode the address (rather, the address tag)
243243
// of an incoming request
244244
addr_decode #(
245-
.NoIndices ( 3 ),
246-
.NoRules ( 4 ),
247-
.addr_t ( paddr_t ),
248-
.rule_t ( rule_t )
245+
.NoIndices(3),
246+
.NoRules (4),
247+
.addr_t (paddr_t),
248+
.rule_t (rule_t)
249249
// .Napot ( 0 )
250250
) i_addr_dec (
251-
.addr_i ( {req_ports_i[i].address_tag, {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}} ),
252-
.addr_map_i ( dcache_spm_map ),
253-
.idx_o ( cur_idx ),
254-
.dec_valid_o ( ),
255-
.dec_error_o ( ),
256-
.en_default_idx_i ( 1'b1 ),
257-
.default_idx_i ( CACHE_REQ )
251+
.addr_i ({req_ports_i[i].address_tag, {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}}),
252+
.addr_map_i (dcache_spm_map),
253+
.idx_o (cur_idx),
254+
.dec_valid_o (),
255+
.dec_error_o (),
256+
.en_default_idx_i(1'b1),
257+
.default_idx_i (CACHE_REQ)
258258
);
259259

260260
always_comb begin
261-
addr_idx_d = addr_idx_q;
262-
addr_tag_d = addr_tag_q;
263-
adec_state_d = adec_state_q;
264-
req_dest_d = req_dest_q;
261+
addr_idx_d = addr_idx_q;
262+
addr_tag_d = addr_tag_q;
263+
adec_state_d = adec_state_q;
264+
req_dest_d = req_dest_q;
265265

266266
// By default we forward all communication to
267267
// all targets, but without the valid and kill signals

‎core/cache_subsystem/wt_cache_subsystem.sv‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -132,26 +132,26 @@ module wt_cache_subsystem
132132
.icache_rtrn_t(icache_rtrn_t),
133133
.RdTxId(0)
134134
) i_cva6_icache (
135-
.clk_i (clk_i),
136-
.rst_ni (rst_ni),
137-
.flush_i (icache_flush_i),
138-
.en_i (icache_en_i),
139-
.miss_o (icache_miss_o),
140-
.busy_o (icache_busy),
141-
.stall_i (stall_i),
142-
.init_ni (init_ni),
135+
.clk_i (clk_i),
136+
.rst_ni (rst_ni),
137+
.flush_i (icache_flush_i),
138+
.en_i (icache_en_i),
139+
.miss_o (icache_miss_o),
140+
.busy_o (icache_busy),
141+
.stall_i (stall_i),
142+
.init_ni (init_ni),
143143
.icache_spm_ways_i('0),
144-
.areq_i (icache_areq_i),
145-
.areq_o (icache_areq_o),
146-
.dreq_i (icache_dreq_i),
147-
.dreq_o (icache_dreq_o),
148-
.ispm_req_i ('0),
149-
.ispm_req_o (),
150-
.mem_rtrn_vld_i(adapter_icache_rtrn_vld),
151-
.mem_rtrn_i (adapter_icache),
152-
.mem_data_req_o(icache_adapter_data_req),
153-
.mem_data_ack_i(adapter_icache_data_ack),
154-
.mem_data_o (icache_adapter)
144+
.areq_i (icache_areq_i),
145+
.areq_o (icache_areq_o),
146+
.dreq_i (icache_dreq_i),
147+
.dreq_o (icache_dreq_o),
148+
.ispm_req_i ('0),
149+
.ispm_req_o (),
150+
.mem_rtrn_vld_i (adapter_icache_rtrn_vld),
151+
.mem_rtrn_i (adapter_icache),
152+
.mem_data_req_o (icache_adapter_data_req),
153+
.mem_data_ack_i (adapter_icache_data_ack),
154+
.mem_data_o (icache_adapter)
155155
);
156156

157157

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