Merge branch 'main' into asap25-release/das

Author: bowwwang

.github/workflows/ci.yml

@@ -247,8 +247,8 @@ jobs:
       run: pip install -r python-requirements.txt
     - name: Build Control Registers
       run: |
-        git submodule update --init --recursive -- hardware/deps/register_interface
-        git apply hardware/deps/patches/register_interface.patch
+        make bender
+        make update-deps
         make -C hardware/src/control_registers clean
         make -C hardware/src/control_registers all
         git diff --ignore-submodules=dirty --exit-code
@@ -259,7 +259,7 @@ jobs:
     - uses: actions/checkout@v4
     - name: Regenerate opcodes
       run: |
-        make update_opcodes
+        make update-opcodes
         git diff --exit-code
 
   ####################
@@ -518,7 +518,7 @@ jobs:
       run: |
         # Don't regenerate previously build artifacts
         sudo apt install device-tree-compiler
-        make update_opcodes
+        make update-opcodes
         touch $GITHUB_WORKSPACE/software/runtime/encoding.h
         touch $GITHUB_WORKSPACE/hardware/src/bootrom.sv
         touch $GITHUB_WORKSPACE/hardware/deps/snitch/src/riscv_instr.sv

.github/workflows/lint.yml

@@ -67,8 +67,10 @@ jobs:
         fi
     - name: Check for trailing whitespaces and tabs
       run: |
-        git diff --check $base HEAD --          \
-            ':(exclude)**.def'                  \
-            ':(exclude)**.patch'                \
-            ':(exclude)toolchain/**'            \
-            ':(exclude)software/riscv-tests/**'
+        git diff --check $base HEAD --                       \
+            ':(exclude)**.def'                               \
+            ':(exclude)**.patch'                             \
+            ':(exclude)toolchain/**'                         \
+            ':(exclude)software/riscv-tests/**'              \
+            ':(exclude)software/runtime/control_registers.h' \
+            ':(exclude)hardware/src/control_registers/*.sv'

.gitlab/.gitlab-ci.yml

@@ -138,7 +138,7 @@ check-control-registers:
 check-opcodes:
   stage: test
   script:
-    - make update_opcodes
+    - make update-opcodes
     - git diff --exit-code
 
 # Software tests
@@ -218,7 +218,7 @@ unit-tests:
     - $CI_PROJECT_DIR/scripts/memora_retry.sh get tc-riscv-gcc
     - $CI_PROJECT_DIR/scripts/memora_retry.sh get riscv-isa-sim
     - $CI_PROJECT_DIR/scripts/memora_retry.sh get verilator-model
-    - make update_opcodes
+    - make update-opcodes
     - touch $ROOT_DIR/software/runtime/encoding.h
     - touch $ROOT_DIR/hardware/src/bootrom.sv
     - touch $ROOT_DIR/hardware/deps/snitch/src/riscv_instr.sv

.gitmodules

@@ -10,39 +10,9 @@
 [submodule "toolchain/verilator"]
 	path = toolchain/verilator
 	url = https://github.com/verilator/verilator.git
-[submodule "hardware/deps/axi"]
-	path = hardware/deps/axi
-	url = https://github.com/pulp-platform/axi.git
-[submodule "hardware/deps/cluster_interconnect"]
-	path = hardware/deps/cluster_interconnect
-	url = https://github.com/pulp-platform/cluster_interconnect.git
-[submodule "hardware/deps/common_cells"]
-	path = hardware/deps/common_cells
-	url = https://github.com/pulp-platform/common_cells.git
-[submodule "hardware/deps/common_verification"]
-	path = hardware/deps/common_verification
-	url = https://github.com/pulp-platform/common_verification.git
-[submodule "hardware/deps/register_interface"]
-	path = hardware/deps/register_interface
-	url = https://github.com/pulp-platform/register_interface.git
-[submodule "hardware/deps/tech_cells_generic"]
-	path = hardware/deps/tech_cells_generic
-	url = https://github.com/pulp-platform/tech_cells_generic.git
 [submodule "toolchain/riscv-opcodes"]
 	path = toolchain/riscv-opcodes
 	url = https://github.com/pulp-platform/riscv-opcodes.git
-[submodule "hardware/deps/apb"]
-	path = hardware/deps/apb
-	url = https://github.com/pulp-platform/apb.git
-[submodule "hardware/deps/fpnew"]
-	path = hardware/deps/fpnew
-	url = https://github.com/pulp-platform/cvfpu.git
-[submodule "hardware/deps/fpu_div_sqrt_mvp"]
-	path = hardware/deps/fpu_div_sqrt_mvp
-	url = https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
 [submodule "hardware/deps/dram_rtl_sim"]
 	path = hardware/deps/dram_rtl_sim
 	url = https://github.com/pulp-platform/dram_rtl_sim.git
-[submodule "hardware/deps/cluster_icache"]
-	path = hardware/deps/cluster_icache
-	url = https://github.com/pulp-platform/cluster_icache.git

CHANGELOG.md

@@ -43,6 +43,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Add fp8 microkernels: axpy, matmul, batchnorm, layernorm, softmax
 - Optimize fp16 matmul kernel
 - Add fall through register after LSU input
+- Benderize MemPool dependencies
+- Update Verilator to 4.228
 
 ### Fixed
 - Fix type issue in `snitch_addr_demux`

Makefile

@@ -240,4 +240,4 @@ format:
 	find ./software/data -name '*.py' -exec autopep8 --in-place --aggressive {} +
 
 clean: clean-riscv-tests clean-deps
-	rm -rf $(INSTALL_DIR)
+	rm -rf $(INSTALL_DIR)

README.md

@@ -8,9 +8,9 @@ This repository branch contains DAS extensions based on MemPool.
 
 # MemPool
 
-MemPool is a many-core system targeting image processing applications. It implements 256 RISC-V cores that can access a large, shared L1 memory in at most five cycles.
+MemPool is a many-core system targeting image processing and wireless applications. It implements 256 RISC-V cores that can access a large, shared L1 memory in at most five cycles. TeraPool and MinPool, respectively a 1024 RISC-V cores scaled-up and a 16 RISC-V cores scaled-down parametrizations of MemPool are also supported.
 
-This repository contains the software and hardware of MemPool, as well as infrastructure for compilation and simulation.
+This repository contains the software and hardware of MinPool, MemPool, and TeraPool, as well as infrastructure for compilation and simulation.
 
 ## Structure
 
@@ -42,12 +42,6 @@ If the repository path of any submodule changes, run the following command to ch
 git submodule sync --recursive
 ```
 
-MemPool requires to patch a few hardware dependencies. To update the dependencies and apply the patches, run the following command after checking out in the project's root directory:
-
-```bash
-make update-deps
-```
-
 ## Build dependencies
 ### Compiler
 
@@ -68,13 +62,20 @@ make halide
 
 ### RTL Simulation
 
-We use [Bender](https://github.com/pulp-platform/bender) to generate our simulation scripts. Make sure you have Bender installed, or install it in the MemPool repository with:
+We use [Bender](https://github.com/pulp-platform/bender) to checkout hardware dependencies and to generate our simulation scripts. Make sure you have Bender installed, or install it in the MemPool repository with:
 
 ```bash
 # Install Bender
 make bender
 ```
 
+To checkout the hardware dependencies using Bender run:
+
+```bash
+# Update hardware dependencies
+make update-deps
+```
+
 The RTL simulation, or more specifically, the tracing in the simulation, relies on the SPIKE simulator. To build it, run the following command in the project's directory:
 
 ```bash
@@ -191,6 +192,22 @@ To get a visualization of the traces, check out the `scripts/tracevis.py` script
 
 We also provide Synopsys Spyglass linting scripts in the `hardware/spyglass`. Run `make lint` in the `hardware` folder, with a specific MemPool configuration, to run the tests associated with the `lint_rtl` target.
 
+## Hardware Configurations
+
+MemPool's core-count is parametrizable. In `./config`, the `config.mk` file includes other configuration files, which represent specific parametrizations of MemPool. We currently support three parametrizations:
+- `terapool`: 1024 cores, organized into 128 tiles with eight cores each
+- `mempool`: 256 cores, organized into 64 tiles with four cores each (default)
+- `minpool`: 16 cores, organized into 4 tiles with four cores each
+
+The software and the hardware for different MemPool configurations can be compiled specifying the desired configuration on the command line. For example, to compile and simulate the `hello_world` app for TeraPool:
+```bash
+cd hardware
+# Compile the hello_world for TeraPool configuration
+config=terapool make COMPILER=gcc hello_world
+# Run the simulation with the *hello_world* binary loaded
+config=terapool app=baremetal/hello_world make sim
+```
+
 ## DRAMsys Co-Simulation
 
 The MemPool system supports both on-chip SRAM or off-chip DRAM co-simulation for higher hierarchy memory transfering. For off-chip DRAM co-simulation, it incorporates the `dram_rtl_sim` tool as a submodule, build at `hardware/deps/dram_rtl_sim`. Leveraging DRAMSys5.0, it facilitates an effective co-simulation environment between RTL models and DRAMSys5.0 for the simulation of DRAM + CTRL models, with contemporary off-chip DRAM technologies (e.g., LPDDR, DDR, HBM).
@@ -225,7 +242,7 @@ For data transfer testing between the MemPool system and higher hierarchy memory
 **Note:** Currently, the simulation crafting tool for off-chip DRAM co-simulation is not open-sourced. We utilize the `Questasim` simulator exclusively.
 
 ## Publications
-If you use MemPool in your work or research, you can cite us:
+If you use MemPool or TeraPool in your work or research, you can cite us:
 
 **MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory**
 
@@ -244,8 +261,23 @@ If you use MemPool in your work or research, you can cite us:
 ```
 This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10227739) and is also available on [arXiv:2303.17742 [cs.AR]](https://arxiv.org/abs/2303.17742) and the [ETH Research Collection](https://doi.org/10.3929/ethz-b-000643341).
 
+**TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-Up Cluster Design With High Bandwidth Main Memory Link**
+
+```
+@article{Zhang2025TeraPool,
+  title={TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-Up Cluster Design With High Bandwidth Main Memory Link},
+  author={Zhang, Yichao and Bertuletti, Marco and Zhang, Chi and Riedel, Samuel and Shen, Diyou and Wang, Bowen and Vanelli-Coralli, Alessandro and Benini, Luca},
+  journal={IEEE Transactions on Computers},
+  year={2025},
+  volume={74},
+  number={11},
+  pages={3667-3681},
+  doi={10.1109/TC.2025.3603692}
+}
+```
+This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/11145329).
 
-The following publications give more details about MemPool, its extensions, and use cases:
+The following publications give more details about MemPool, TeraPool, its extensions, and use cases:
 
 ### 2021
 
@@ -631,6 +663,29 @@ This paper is available on [IEEE Xplore](https://ieeexplore.ieee.org/document/10
 ```
 This paper is available on [ACM DIGITAL LIBRARY](https://dl.acm.org/doi/10.1145/3649476.3658735).
 
+### 2025
+
+</p>
+</details>
+
+<details>
+<summary><i>A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks</i></summary>
+<p>
+
+```
+@article{Bertuletti2025TeraPool,
+  title={A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks},
+  author={Bertuletti, Marco and Zhang, Yichao and Vanelli-Coralli, Alessandro and Benini, Luca},
+  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  year={2025},
+  volume={33},
+  number={8},
+  pages={2225-2238},
+  doi={10.1109/TVLSI.2025.3576855}
+}
+```
+This paper is available on [IEEE Xplore](https://ieeexplore.ieee.org/abstract/document/11038837).
+
 </p>
 </details>