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feat: implement halt-on-reset (resethaltreq) - #188

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feat: implement halt-on-reset (resethaltreq)#188
siju-felsite wants to merge 1 commit into
pulp-platform:masterfrom
siju-felsite:resethaltreq-impl

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@siju-felsite

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Closes #187.

Implements the halt-on-reset sequence so a debugger can halt a hart at its first instruction out of reset (needed for early-boot / secure-boot / ROM debugging, where a software ebreak can't be planted).

What changed

  • dm_csrs.sv: dmstatus.hasresethaltreq = 1; per-hart resethaltreq state backed by dmcontrol.set/clrresethaltreq (applied to the hart selected by the same write); survives ndmreset, cleared on PoR / dmactive=0.
    • dm_mem.sv: per-hart resethaltpend armed while a hart is held in ndmreset with resethaltreq set, held across reset deassert until the hart reports halted (or the request is cleared); debug_req_o = haltreq_i | resethaltpend_q.
    • dm_top.sv: wires the new signal dm_csrs -> dm_mem internally.
      Routed through the existing debug_req_o rather than adding a new dm_top output, so the module interface is unchanged and existing integrators get halt-on-reset with no wiring changes (verified: dm_obi_top needs no edits and still elaborates). Happy to also expose a status output if you'd prefer.

Scope / limitation

Enforced for ndmreset (which the DM survives, being in the always-on domain); a full PoR that also resets the DM clears resethaltreq and the debugger re-arms — inherent to the DM's view of resets. dmcontrol.hartreset remains hardwired 0.

Testing

  • Elaborates latch-free under Verilator with zero new warnings vs. baseline.
    • Directed self-checking testbench (drives the DMI side, models the hart-side halt handshake): NrHarts=1 10/10 and NrHarts=2 14/14 — covers hasresethaltreq=1, debug_req held across ndmreset then dropped once halted (so resume works), re-arm on a second reset (not one-shot), clrresethaltreq cancels, and per-hart independence. Glad to contribute the testbench if useful.
    • Behavior is unchanged when inactive (resethaltreq==0 => debug_req_o == haltreq_i). The full OpenOCD/cv32e40p core-in-the-loop regression runs in CI.
      Developed with AI assistance (design + draft); I have reviewed and tested the entire change.

Back dmcontrol.set/clrresethaltreq with per-hart resethaltreq state, set dmstatus.hasresethaltreq=1, and hold debug_req across ndmreset deassert until the hart enters debug. Routed through the existing debug_req_o, so dm_top's interface is unchanged.
@phsauter

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Its not a big diff but it will take me some time to review. I am quite busy the next 10 days and I will need to read up on the spec to properly judge this.
So if you need it in the meantime you may need to go with a fork/local version for now.

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Halt-on-reset (resethaltreq) not implemented — hasresethaltreq hardwired 0, no dm_top port

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