feat: implement halt-on-reset (resethaltreq) - #188
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Back dmcontrol.set/clrresethaltreq with per-hart resethaltreq state, set dmstatus.hasresethaltreq=1, and hold debug_req across ndmreset deassert until the hart enters debug. Routed through the existing debug_req_o, so dm_top's interface is unchanged.
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Its not a big diff but it will take me some time to review. I am quite busy the next 10 days and I will need to read up on the spec to properly judge this. |
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Closes #187.
Implements the halt-on-reset sequence so a debugger can halt a hart at its first instruction out of reset (needed for early-boot / secure-boot / ROM debugging, where a software
ebreakcan't be planted).What changed
dm_csrs.sv:dmstatus.hasresethaltreq = 1; per-hartresethaltreqstate backed bydmcontrol.set/clrresethaltreq(applied to the hart selected by the same write); survivesndmreset, cleared on PoR /dmactive=0.dm_mem.sv: per-hartresethaltpendarmed while a hart is held inndmresetwithresethaltreqset, held across reset deassert until the hart reports halted (or the request is cleared);debug_req_o = haltreq_i | resethaltpend_q.dm_top.sv: wires the new signaldm_csrs->dm_meminternally.Routed through the existing
debug_req_orather than adding a newdm_topoutput, so the module interface is unchanged and existing integrators get halt-on-reset with no wiring changes (verified:dm_obi_topneeds no edits and still elaborates). Happy to also expose a status output if you'd prefer.Scope / limitation
Enforced for
ndmreset(which the DM survives, being in the always-on domain); a full PoR that also resets the DM clearsresethaltreqand the debugger re-arms — inherent to the DM's view of resets.dmcontrol.hartresetremains hardwired 0.Testing
NrHarts=110/10 andNrHarts=214/14 — covershasresethaltreq=1,debug_reqheld acrossndmresetthen dropped once halted (so resume works), re-arm on a second reset (not one-shot),clrresethaltreqcancels, and per-hart independence. Glad to contribute the testbench if useful.resethaltreq==0=>debug_req_o == haltreq_i). The full OpenOCD/cv32e40p core-in-the-loop regression runs in CI.Developed with AI assistance (design + draft); I have reviewed and tested the entire change.