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fischetifischeti
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chore: dependency and python bump (#26)
1 parent d4e513a commit 3fbad0a

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Lines changed: 108 additions & 96 deletions

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‎.github/dependabot.yml‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
# Copyright 2024 ETH Zurich and University of Bologna.
2+
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
3+
# SPDX-License-Identifier: SHL-0.51
4+
5+
version: 2
6+
updates:
7+
# Python dependencies managed by uv (pyproject.toml + uv.lock)
8+
- package-ecosystem: "uv"
9+
directory: "/"
10+
schedule:
11+
interval: "weekly"
12+
cooldown:
13+
default-days: 7
14+
groups:
15+
python-deps:
16+
patterns: ["*"]
17+
18+
# GitHub Actions used in .github/workflows
19+
- package-ecosystem: "github-actions"
20+
directory: "/"
21+
schedule:
22+
interval: "weekly"
23+
cooldown:
24+
default-days: 7
25+
groups:
26+
github-actions:
27+
patterns: ["*"]

‎.gitlab-ci.yml‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,6 @@ variables:
99

1010
before_script:
1111
- ln -sf .iis_env .env
12-
- /usr/local/uv/uv tool install rust-just --quiet
13-
- export PATH="${HOME}/.local/bin:${PATH}"
1412

1513
stages:
1614
- build

‎.iis_env‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,4 +10,4 @@ VSIM="questa-2025.1 vsim"
1010
VCS="vcs-2025.06 vcs"
1111
VLOGAN="vcs-2025.06 vlogan"
1212
PEAKRDL="/usr/local/uv/uv run peakrdl"
13-
BENDER="bender-0.31.0"
13+
BENDER="bender-0.32.0"

‎.python-version‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
3.11
1+
3.14

‎pyproject.toml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,5 +10,5 @@ readme = "README.md"
1010
requires-python = ">=3.11"
1111
dependencies = [
1212
"peakrdl>=1.5.0",
13-
"peakrdl-rawheader>=0.1.1",
13+
"peakrdl-rawheader>=0.2.5",
1414
]

‎src/regs/slink_addrmap.svh‎

Lines changed: 31 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -2,72 +2,59 @@
22
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
33
// SPDX-License-Identifier: SHL-0.51
44

5+
// Generated by PeakRDL raw-header
6+
57
`ifndef SLINK_REG_SVH
68
`define SLINK_REG_SVH
79

10+
`define SLINK_REG_BASE_ADDR 64'h0
11+
`define SLINK_REG_SIZE 64'h804
812

9-
`define SLINK_REG_BASE_ADDR 64'h00000000
10-
`define SLINK_REG_SIZE 64'h00000804
11-
12-
`define SLINK_REG_CTRL_REG_ADDR 64'h00000000
13-
`define SLINK_REG_CTRL_REG_OFFSET 64'h00000000
14-
15-
`define SLINK_REG_ISOLATED_REG_ADDR 64'h00000004
16-
`define SLINK_REG_ISOLATED_REG_OFFSET 64'h00000004
13+
`define SLINK_REG_CTRL_BASE_ADDR 64'h0
1714

18-
`define SLINK_REG_RAW_MODE_EN_REG_ADDR 64'h00000008
19-
`define SLINK_REG_RAW_MODE_EN_REG_OFFSET 64'h00000008
15+
`define SLINK_REG_ISOLATED_BASE_ADDR 64'h4
2016

21-
`define SLINK_REG_RAW_MODE_IN_DATA_REG_ADDR 64'h0000000C
22-
`define SLINK_REG_RAW_MODE_IN_DATA_REG_OFFSET 64'h0000000C
17+
`define SLINK_REG_RAW_MODE_EN_BASE_ADDR 64'h8
2318

24-
`define SLINK_REG_RAW_MODE_IN_CH_SEL_REG_ADDR 64'h00000010
25-
`define SLINK_REG_RAW_MODE_IN_CH_SEL_REG_OFFSET 64'h00000010
19+
`define SLINK_REG_RAW_MODE_IN_DATA_BASE_ADDR 64'hC
2620

27-
`define SLINK_REG_RAW_MODE_OUT_DATA_FIFO_REG_ADDR 64'h00000014
28-
`define SLINK_REG_RAW_MODE_OUT_DATA_FIFO_REG_OFFSET 64'h00000014
21+
`define SLINK_REG_RAW_MODE_IN_CH_SEL_BASE_ADDR 64'h10
2922

30-
`define SLINK_REG_RAW_MODE_OUT_DATA_FIFO_CTRL_REG_ADDR 64'h00000018
31-
`define SLINK_REG_RAW_MODE_OUT_DATA_FIFO_CTRL_REG_OFFSET 64'h00000018
23+
`define SLINK_REG_RAW_MODE_OUT_DATA_FIFO_BASE_ADDR 64'h14
3224

33-
`define SLINK_REG_RAW_MODE_OUT_EN_REG_ADDR 64'h0000001C
34-
`define SLINK_REG_RAW_MODE_OUT_EN_REG_OFFSET 64'h0000001C
25+
`define SLINK_REG_RAW_MODE_OUT_DATA_FIFO_CTRL_BASE_ADDR 64'h18
3526

36-
`define SLINK_REG_FLOW_CONTROL_FIFO_CLEAR_REG_ADDR 64'h00000020
37-
`define SLINK_REG_FLOW_CONTROL_FIFO_CLEAR_REG_OFFSET 64'h00000020
27+
`define SLINK_REG_RAW_MODE_OUT_EN_BASE_ADDR 64'h1C
3828

39-
`define SLINK_REG_RAW_MODE_IN_DATA_VALID_0_REG_ADDR 64'h00000100
40-
`define SLINK_REG_RAW_MODE_IN_DATA_VALID_0_REG_OFFSET 64'h00000100
29+
`define SLINK_REG_FLOW_CONTROL_FIFO_CLEAR_BASE_ADDR 64'h20
4130

42-
`define SLINK_REG_RAW_MODE_OUT_CH_MASK_0_REG_ADDR 64'h00000200
43-
`define SLINK_REG_RAW_MODE_OUT_CH_MASK_0_REG_OFFSET 64'h00000200
31+
`define SLINK_REG_RAW_MODE_IN_DATA_VALID_BASE_ADDR(raw_mode_in_data_valid_idx) (64'h100 + (raw_mode_in_data_valid_idx * 64'h4) )
32+
`define SLINK_REG_RAW_MODE_IN_DATA_VALID_NUM 64'h1
4433

45-
`define SLINK_REG_TX_PHY_CLK_DIV_0_REG_ADDR 64'h00000300
46-
`define SLINK_REG_TX_PHY_CLK_DIV_0_REG_OFFSET 64'h00000300
34+
`define SLINK_REG_RAW_MODE_OUT_CH_MASK_BASE_ADDR(raw_mode_out_ch_mask_idx) (64'h200 + (raw_mode_out_ch_mask_idx * 64'h4) )
35+
`define SLINK_REG_RAW_MODE_OUT_CH_MASK_NUM 64'h1
4736

48-
`define SLINK_REG_TX_PHY_CLK_START_0_REG_ADDR 64'h00000400
49-
`define SLINK_REG_TX_PHY_CLK_START_0_REG_OFFSET 64'h00000400
37+
`define SLINK_REG_TX_PHY_CLK_DIV_BASE_ADDR(tx_phy_clk_div_idx) (64'h300 + (tx_phy_clk_div_idx * 64'h4) )
38+
`define SLINK_REG_TX_PHY_CLK_DIV_NUM 64'h1
5039

51-
`define SLINK_REG_TX_PHY_CLK_END_0_REG_ADDR 64'h00000500
52-
`define SLINK_REG_TX_PHY_CLK_END_0_REG_OFFSET 64'h00000500
40+
`define SLINK_REG_TX_PHY_CLK_START_BASE_ADDR(tx_phy_clk_start_idx) (64'h400 + (tx_phy_clk_start_idx * 64'h4) )
41+
`define SLINK_REG_TX_PHY_CLK_START_NUM 64'h1
5342

54-
`define SLINK_REG_CHANNEL_ALLOC_TX_CFG_REG_ADDR 64'h00000600
55-
`define SLINK_REG_CHANNEL_ALLOC_TX_CFG_REG_OFFSET 64'h00000600
43+
`define SLINK_REG_TX_PHY_CLK_END_BASE_ADDR(tx_phy_clk_end_idx) (64'h500 + (tx_phy_clk_end_idx * 64'h4) )
44+
`define SLINK_REG_TX_PHY_CLK_END_NUM 64'h1
5645

57-
`define SLINK_REG_CHANNEL_ALLOC_TX_CTRL_REG_ADDR 64'h00000604
58-
`define SLINK_REG_CHANNEL_ALLOC_TX_CTRL_REG_OFFSET 64'h00000604
46+
`define SLINK_REG_CHANNEL_ALLOC_TX_CFG_BASE_ADDR 64'h600
5947

60-
`define SLINK_REG_CHANNEL_ALLOC_RX_CFG_REG_ADDR 64'h00000608
61-
`define SLINK_REG_CHANNEL_ALLOC_RX_CFG_REG_OFFSET 64'h00000608
48+
`define SLINK_REG_CHANNEL_ALLOC_TX_CTRL_BASE_ADDR 64'h604
6249

63-
`define SLINK_REG_CHANNEL_ALLOC_RX_CTRL_REG_ADDR 64'h0000060C
64-
`define SLINK_REG_CHANNEL_ALLOC_RX_CTRL_REG_OFFSET 64'h0000060C
50+
`define SLINK_REG_CHANNEL_ALLOC_RX_CFG_BASE_ADDR 64'h608
6551

66-
`define SLINK_REG_CHANNEL_ALLOC_TX_CH_EN_0_REG_ADDR 64'h00000700
67-
`define SLINK_REG_CHANNEL_ALLOC_TX_CH_EN_0_REG_OFFSET 64'h00000700
52+
`define SLINK_REG_CHANNEL_ALLOC_RX_CTRL_BASE_ADDR 64'h60C
6853

69-
`define SLINK_REG_CHANNEL_ALLOC_RX_CH_EN_0_REG_ADDR 64'h00000800
70-
`define SLINK_REG_CHANNEL_ALLOC_RX_CH_EN_0_REG_OFFSET 64'h00000800
54+
`define SLINK_REG_CHANNEL_ALLOC_TX_CH_EN_BASE_ADDR(channel_alloc_tx_ch_en_idx) (64'h700 + (channel_alloc_tx_ch_en_idx * 64'h4) )
55+
`define SLINK_REG_CHANNEL_ALLOC_TX_CH_EN_NUM 64'h1
7156

57+
`define SLINK_REG_CHANNEL_ALLOC_RX_CH_EN_BASE_ADDR(channel_alloc_rx_ch_en_idx) (64'h800 + (channel_alloc_rx_ch_en_idx * 64'h4) )
58+
`define SLINK_REG_CHANNEL_ALLOC_RX_CH_EN_NUM 64'h1
7259

7360
`endif /* SLINK_REG_SVH */

‎test/tb_axi_slink.sv‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -429,18 +429,18 @@ module tb_axi_slink;
429429
$info("[DDR%0d]: Enabling clock and deassert link reset.", id);
430430
// Reset and clock gate sequence, AXI isolation remains enabled
431431
// De-assert reset
432-
cfg_write(drv, `SLINK_REG_CTRL_REG_OFFSET, 32'h300);
432+
cfg_write(drv, `SLINK_REG_CTRL_BASE_ADDR, 32'h300);
433433
// Assert reset
434-
cfg_write(drv, `SLINK_REG_CTRL_REG_OFFSET, 32'h302);
434+
cfg_write(drv, `SLINK_REG_CTRL_BASE_ADDR, 32'h302);
435435
// Enable clock
436-
cfg_write(drv, `SLINK_REG_CTRL_REG_OFFSET, 32'h303);
436+
cfg_write(drv, `SLINK_REG_CTRL_BASE_ADDR, 32'h303);
437437
// Wait for some clock cycles
438438
repeat(50) drv.cycle_end();
439439
// De-isolate AXI ports
440440
$info("[DDR%0d] Enabling AXI ports...",id);
441-
cfg_write(drv, `SLINK_REG_CTRL_REG_OFFSET, 32'h03);
441+
cfg_write(drv, `SLINK_REG_CTRL_BASE_ADDR, 32'h03);
442442
do begin
443-
cfg_read(drv, `SLINK_REG_ISOLATED_REG_OFFSET, data);
443+
cfg_read(drv, `SLINK_REG_ISOLATED_BASE_ADDR, data);
444444
end while(data != 0); // Wait until both isolation status bits are 0 to
445445
// indicate disabling of isolation
446446
$info("[DDR%0d] Link is ready", id);

‎test/tb_ch_calib_slink.sv‎

Lines changed: 38 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -454,11 +454,11 @@ module tb_ch_calib_slink;
454454
$info("[DDR%0d]: Enabling clock and deassert link reset.", id);
455455
// Reset and clock gate sequence, AXI isolation remains enabled
456456
// De-assert reset
457-
cfg_write(drv, `SLINK_REG_CTRL_REG_OFFSET, 32'h300);
457+
cfg_write(drv, `SLINK_REG_CTRL_BASE_ADDR, 32'h300);
458458
// Assert reset
459-
cfg_write(drv, `SLINK_REG_CTRL_REG_OFFSET, 32'h302);
459+
cfg_write(drv, `SLINK_REG_CTRL_BASE_ADDR, 32'h302);
460460
// Enable clock
461-
cfg_write(drv, `SLINK_REG_CTRL_REG_OFFSET, 32'h303);
461+
cfg_write(drv, `SLINK_REG_CTRL_BASE_ADDR, 32'h303);
462462
endtask
463463

464464
task automatic calibrate_link(apb_master_t drv, int id);
@@ -479,70 +479,70 @@ module tb_ch_calib_slink;
479479
// isolated before the master out port on the other side. Otherwise there might
480480
// transactions in flight that get lost
481481
$info("[DDR%0d]: Isolating AXI Slave In", id);
482-
cfg_write(drv, `SLINK_REG_CTRL_REG_OFFSET, 32'h103);
482+
cfg_write(drv, `SLINK_REG_CTRL_BASE_ADDR, 32'h103);
483483
do begin
484-
cfg_read(drv, `SLINK_REG_ISOLATED_REG_OFFSET, data);
484+
cfg_read(drv, `SLINK_REG_ISOLATED_BASE_ADDR, data);
485485
end while(data[0] != 1'b1); // Wait until isolation status bit is 1
486486
$info("[DDR%0d]: Isolated AXI Slave In", id);
487487
// Wait for a few clock cycles before isolating AXI Master out
488488
repeat(100) @(posedge clk_reg);
489489
$info("[DDR%0d]: Isolating AXI Master Out", id);
490-
cfg_write(drv, `SLINK_REG_CTRL_REG_OFFSET, 32'h303);
490+
cfg_write(drv, `SLINK_REG_CTRL_BASE_ADDR, 32'h303);
491491
do begin
492-
cfg_read(drv, `SLINK_REG_ISOLATED_REG_OFFSET, data);
492+
cfg_read(drv, `SLINK_REG_ISOLATED_BASE_ADDR, data);
493493
end while(data[1:0] != 2'b11); // Wait until both isolation status bit is are 1
494494
$info("[DDR%0d]: Isolated AXI Master Out", id);
495495
// Configure Raw Mode
496496
$info("[DDR%0d]: Preparing link for calibration...",id);
497497
// Prepare channel allocator for RAW mode
498498
// Enable bypass mode and auto flush feature but disable sync for RX side
499-
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_TX_CFG_REG_OFFSET, 32'h3);
500-
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_RX_CFG_REG_OFFSET, 32'h3);
499+
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_TX_CFG_BASE_ADDR, 32'h3);
500+
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_RX_CFG_BASE_ADDR, 32'h3);
501501
// Enable Raw Mode
502-
cfg_write(drv, `SLINK_REG_RAW_MODE_EN_REG_OFFSET, 1);
502+
cfg_write(drv, `SLINK_REG_RAW_MODE_EN_BASE_ADDR, 1);
503503
// Set mask for sending out pattern
504504
for (int i = 0; i < NumChannels; i++) begin
505-
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_CH_MASK_0_REG_OFFSET + i * 4, 1);
505+
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_CH_MASK_BASE_ADDR(i), 1);
506506
end
507507
for (int i = 0; i < NumChannels; i++) begin
508508
// Enable same channels in TX side of channel allocator
509-
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_TX_CH_EN_0_REG_OFFSET + i * 4, 1);
510-
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_RX_CH_EN_0_REG_OFFSET + i * 4, 1);
509+
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_TX_CH_EN_BASE_ADDR(i), 1);
510+
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_RX_CH_EN_BASE_ADDR(i), 1);
511511
end
512512
$info("[DDR%0d]: Sending calibration sequence", id);
513513
// Clear the TX Fifo
514-
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_DATA_FIFO_CTRL_REG_OFFSET, 32'h1);
515-
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_DATA_FIFO_CTRL_REG_OFFSET, 32'h0);
514+
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_DATA_FIFO_CTRL_BASE_ADDR, 32'h1);
515+
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_DATA_FIFO_CTRL_BASE_ADDR, 32'h0);
516516
// Send a pattern sequence to TX FIFO
517517
for (int i = 0; i < 8; i++) begin
518518
pattern = 16'haaaa << i;
519519
pattern_q.push_back(pattern);
520-
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_DATA_FIFO_REG_OFFSET, pattern);
520+
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_DATA_FIFO_BASE_ADDR, pattern);
521521
end
522522
// Send out pattern
523-
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_EN_REG_OFFSET, 1);
523+
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_EN_BASE_ADDR, 1);
524524
// Wait until some channels have received data
525525
do begin
526526
for (int i = 0; i < NumChannels; i++) begin
527-
cfg_read(drv, `SLINK_REG_RAW_MODE_IN_DATA_VALID_0_REG_OFFSET + i * 4, data);
527+
cfg_read(drv, `SLINK_REG_RAW_MODE_IN_DATA_VALID_BASE_ADDR(i), data);
528528
raw_mode_data_in_valid[i] = data[0];
529529
end
530530
end while(raw_mode_data_in_valid[NumChannels-1:0] == 0);
531531
// Iterate through every channel
532532
for (int c = 0; c < NumChannels; c++) begin
533533
// Select read channel
534-
cfg_write(drv, `SLINK_REG_RAW_MODE_IN_CH_SEL_REG_OFFSET, c);
534+
cfg_write(drv, `SLINK_REG_RAW_MODE_IN_CH_SEL_BASE_ADDR, c);
535535
// Check read patterns
536536
foreach(pattern_q[i]) begin
537537
// Check first that there is valid data in the RX FIFO
538-
cfg_read(drv, `SLINK_REG_RAW_MODE_IN_DATA_VALID_0_REG_OFFSET + c * 4, data);
538+
cfg_read(drv, `SLINK_REG_RAW_MODE_IN_DATA_VALID_BASE_ADDR(c), data);
539539
if (data == 1'b0) begin
540540
$info("[DDR%0d][CH%0d] No data in RX FIFO", id, c);
541541
working_rx_channels[c] = 1'b0;
542542
break;
543543
end
544544
// Read out first pattern
545-
cfg_read(drv, `SLINK_REG_RAW_MODE_IN_DATA_REG_OFFSET, data);
545+
cfg_read(drv, `SLINK_REG_RAW_MODE_IN_DATA_BASE_ADDR, data);
546546
if (pattern_q[i] != data) begin
547547
$error("[DDR%0d][CH%0d] Pattern missmatch actual %h data expected %h",
548548
id, c, data, pattern_q[i]);
@@ -560,73 +560,73 @@ module tb_ch_calib_slink;
560560
// Check that there is no more valid data in the RX FIFOs
561561
// of all working channels
562562
for (int i = 0; i < NumChannels; i++) begin
563-
cfg_read(drv, `SLINK_REG_RAW_MODE_IN_DATA_VALID_0_REG_OFFSET, data);
563+
cfg_read(drv, `SLINK_REG_RAW_MODE_IN_DATA_VALID_BASE_ADDR(i), data);
564564
raw_mode_data_in_valid[i] = data[0];
565565
end
566566
assert ((raw_mode_data_in_valid[NumChannels-1:0] & working_rx_channels) == '0) else begin
567567
$error("[DDR%0d] Still data in RX FIFO %s", id, print_ch_mask(data & working_rx_channels));
568568
end
569569
// Clear the TX Fifo
570-
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_DATA_FIFO_CTRL_REG_OFFSET, 32'h1);
571-
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_DATA_FIFO_CTRL_REG_OFFSET, 32'h0);
570+
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_DATA_FIFO_CTRL_BASE_ADDR, 32'h1);
571+
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_DATA_FIFO_CTRL_BASE_ADDR, 32'h0);
572572
// Wait for some time to make sure that the other side has handled calibration as well
573573
repeat(500) @(posedge clk_reg);
574574
// Load the channel mask of working channels into TX FIFO
575575
// They should be immediately sent as TX FIFO is still enabled
576576
$info("[DDR%0d] Sending out RX channel mask.", id);
577577
for (int i = 0; i < (NumChannels + ChMaskBitsPerCycle - 1)/ChMaskBitsPerCycle; i++) begin
578578
// Write the channel mask into the TX FIFO
579-
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_DATA_FIFO_REG_OFFSET, {'0, working_rx_channels[ChMaskBitsPerCycle*i+:ChMaskBitsPerCycle]});
579+
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_DATA_FIFO_BASE_ADDR, {'0, working_rx_channels[ChMaskBitsPerCycle*i+:ChMaskBitsPerCycle]});
580580
end
581581
// Wait until the channel mask from the other side has arrived
582582
do begin
583583
for (int i = 0; i < NumChannels; i++) begin
584-
cfg_read(drv, `SLINK_REG_RAW_MODE_IN_DATA_VALID_0_REG_OFFSET + i * 4, data);
584+
cfg_read(drv, `SLINK_REG_RAW_MODE_IN_DATA_VALID_BASE_ADDR(i), data);
585585
raw_mode_data_in_valid[i] = data[0];
586586
end
587587
end while(raw_mode_data_in_valid[NumChannels-1:0] == 0);
588588
// Only check RX channels that are working
589589
for (int c = 0; c < NumChannels; c++) begin
590590
if (working_rx_channels[c]) begin
591591
// Select channel to read from
592-
cfg_write(drv, `SLINK_REG_RAW_MODE_IN_CH_SEL_REG_OFFSET, c);
592+
cfg_write(drv, `SLINK_REG_RAW_MODE_IN_CH_SEL_BASE_ADDR, c);
593593
// Read the mask
594594
for (int i = 0; i < (NumChannels + ChMaskBitsPerCycle - 1)/ChMaskBitsPerCycle; i++) begin
595-
cfg_read(drv, `SLINK_REG_RAW_MODE_IN_DATA_REG_OFFSET, working_tx_channels[ChMaskBitsPerCycle*i+:ChMaskBitsPerCycle]);
595+
cfg_read(drv, `SLINK_REG_RAW_MODE_IN_DATA_BASE_ADDR, working_tx_channels[ChMaskBitsPerCycle*i+:ChMaskBitsPerCycle]);
596596
end
597597
end
598598
end
599599
$info("[DDR%0d] TX channel mask %s", id, print_ch_mask(working_tx_channels));
600600
// Disable TX Fifo
601-
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_EN_REG_OFFSET, 0);
601+
cfg_write(drv, `SLINK_REG_RAW_MODE_OUT_EN_BASE_ADDR, 0);
602602
// Enable RX/TX channels
603603
for (int i = 0; i < NumChannels; i++) begin
604-
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_TX_CH_EN_0_REG_OFFSET + 4 * i, working_tx_channels[i]);
605-
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_RX_CH_EN_0_REG_OFFSET + 4 * i, working_rx_channels[i]);
604+
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_TX_CH_EN_BASE_ADDR(i), working_tx_channels[i]);
605+
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_RX_CH_EN_BASE_ADDR(i), working_rx_channels[i]);
606606
end
607607
// Configure channel allocator
608608
// Set auto-flush count value == 2
609609
if ($countones(working_tx_channels) == NumChannels) begin
610610
// Enable bypass
611-
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_TX_CFG_REG_OFFSET, 32'h203);
611+
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_TX_CFG_BASE_ADDR, 32'h203);
612612
end else begin
613613
// Disable bypass
614-
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_TX_CFG_REG_OFFSET, 32'h202);
614+
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_TX_CFG_BASE_ADDR, 32'h202);
615615
end
616616
// Set auto-flush count value == 2 and re-enable RX synchronization
617617
if ($countones(working_rx_channels) == NumChannels) begin
618-
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_RX_CFG_REG_OFFSET, 32'h10203);
618+
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_RX_CFG_BASE_ADDR, 32'h10203);
619619
end else begin
620-
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_RX_CFG_REG_OFFSET, 32'h10202);
620+
cfg_write(drv, `SLINK_REG_CHANNEL_ALLOC_RX_CFG_BASE_ADDR, 32'h10202);
621621
end
622622
// Configure normal operating mode
623-
cfg_write(drv, `SLINK_REG_RAW_MODE_EN_REG_OFFSET, 0);
623+
cfg_write(drv, `SLINK_REG_RAW_MODE_EN_BASE_ADDR, 0);
624624
// Wait for the other Serial Link to be ready
625625
repeat(100) @(posedge clk_reg);
626626
$info("[DDR%0d] Enabling AXI ports...",id);
627-
cfg_write(drv, `SLINK_REG_CTRL_REG_OFFSET, 32'h03);
627+
cfg_write(drv, `SLINK_REG_CTRL_BASE_ADDR, 32'h03);
628628
do begin
629-
cfg_read(drv, `SLINK_REG_ISOLATED_REG_OFFSET, data);
629+
cfg_read(drv, `SLINK_REG_ISOLATED_BASE_ADDR, data);
630630
end while(data != 0); // Wait until both isolation status bits are 0 to
631631
// indicate disabling of isolation
632632
$info("[DDR%0d] Link is ready", id);

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