treewide: Update toolchain flags for minimal, auto-generated toolchain

Author: colluca

iis-setup.sh

@@ -12,7 +12,7 @@ export SN_VCS_SEPP=vcs-2024.09
 export SN_VERILATOR_SEPP=$SN_OSEDA
 export SN_QUESTA_SEPP=questa-2023.4
 export SN_YOSYS="$SN_OSEDA yosys"
-export SN_LLVM_BINROOT=/usr/scratch2/vulcano/colluca/tools/riscv32-snitch-llvm-almalinux8-15.0.0-snitch-0.5.0/bin
+export SN_LLVM_BINROOT=/scratch2/colluca/workspace/REPOS/LLVM_PROJECT/install/bin/
 
 # We need Make >4.3 for grouped targets
 export PATH=$PWD/util/bin:$PATH

make/common.mk

@@ -24,8 +24,6 @@ SN_BENDER         ?= bender
 SN_PEAKRDL        ?= peakrdl
 SN_VERIBLE_FMT    ?= verible-verilog-format
 SN_CLANG_FORMAT   ?= $(SN_LLVM_BINROOT)/clang-format
-SN_RISCV_MC       ?= $(SN_LLVM_BINROOT)/llvm-mc
-SN_ADDR2LINE      ?= $(SN_LLVM_BINROOT)/llvm-addr2line
 # tail is required for nonsense oseda output
 SN_VERILATOR_SEPP ?=
 SN_VLT_BIN         = $(shell $(SN_VERILATOR_SEPP) which verilator_bin | tail -n1 | $(SN_VERILATOR_SEPP) xargs realpath | tail -n1)
@@ -57,10 +55,6 @@ SN_BENDER_YML  = $(SN_ROOT)/Bender.yml
 # Flags
 SN_COMMON_BENDER_FLAGS     += -t rtl -t snitch_cluster
 SN_COMMON_BENDER_SIM_FLAGS += -t simulation -t test
-SN_MCPU                    ?= snitch
-SN_RISCV_MC_FLAGS          ?= -disassemble
-SN_RISCV_MC_FLAGS          += -mcpu=$(SN_MCPU)
-SN_ANNOTATE_FLAGS          ?= -q --keep-time --addr2line=$(SN_ADDR2LINE)
 SN_LAYOUT_EVENTS_FLAGS     ?= --cfg=$(SN_CFG)
 
 # Internal state

make/traces.mk

@@ -4,10 +4,6 @@
 #
 # Luca Colagrande <colluca@iis.ee.ethz.ch>
 
-##########
-# Traces #
-##########
-
 # Reads the binary from the logs/.rtlbinary file that is written at start
 # of simulation in the vsim script
 SN_BINARY ?= $(shell cat $(SN_SIM_DIR)/.rtlbinary)
@@ -22,7 +18,9 @@ SN_JOINT_PERF_DUMP  = $(SN_LOGS_DIR)/perf.json
 SN_ROI_DUMP         = $(SN_LOGS_DIR)/roi.json
 SN_VISUAL_TRACE     = $(SN_LOGS_DIR)/trace.json
 
-SN_VISUALIZE_PY_FLAGS += --tracevis "$(SN_BINARY) $(SN_TXT_TRACES) --addr2line $(SN_ADDR2LINE) -f snitch"
+SN_RISCV_MC_FLAGS     ?= -disassemble $(SN_RISCV_MATTR_FLAG)
+SN_ANNOTATE_FLAGS     ?= -q --keep-time --addr2line=$(SN_RISCV_ADDR2LINE)
+SN_VISUALIZE_PY_FLAGS += --tracevis "$(SN_BINARY) $(SN_TXT_TRACES) --addr2line $(SN_RISCV_ADDR2LINE) -f snitch"
 SN_GENTRACE_PY_FLAGS  += --mc-exec $(SN_RISCV_MC) --mc-flags "$(SN_RISCV_MC_FLAGS)"
 
 # Do not suspend trace generation upon gentrace errors when debugging

sw/toolchain.mk

@@ -5,26 +5,39 @@
 # Luca Colagrande <colluca@iis.ee.ethz.ch>
 # Viviane Potocnik <vivianep@iis.ee.ethz.ch>
 
+########
+# Util #
+########
+
+empty :=
+space := $(empty) $(empty)
+comma := ,
+
+comma-join = $(subst $(space),$(comma),$(strip $(1)))
+
 ###################
 # Build variables #
 ###################
 
 # Compiler toolchain
-SN_LLVM_BINROOT  ?= $(dir $(shell which riscv32-unknown-elf-clang))
-SN_RISCV_CC      ?= $(SN_LLVM_BINROOT)/clang
-SN_RISCV_CXX     ?= $(SN_LLVM_BINROOT)/clang++
-SN_RISCV_LD      ?= $(SN_LLVM_BINROOT)/ld.lld
-SN_RISCV_AR      ?= $(SN_LLVM_BINROOT)/llvm-ar
-SN_RISCV_OBJCOPY ?= $(SN_LLVM_BINROOT)/llvm-objcopy
-SN_RISCV_OBJDUMP ?= $(SN_LLVM_BINROOT)/llvm-objdump
+SN_LLVM_BINROOT    ?= $(dir $(shell which riscv32-unknown-elf-clang))
+SN_RISCV_CC        ?= $(SN_LLVM_BINROOT)/clang
+SN_RISCV_CXX       ?= $(SN_LLVM_BINROOT)/clang++
+SN_RISCV_LD        ?= $(SN_LLVM_BINROOT)/ld.lld
+SN_RISCV_AR        ?= $(SN_LLVM_BINROOT)/llvm-ar
+SN_RISCV_OBJCOPY   ?= $(SN_LLVM_BINROOT)/llvm-objcopy
+SN_RISCV_OBJDUMP   ?= $(SN_LLVM_BINROOT)/llvm-objdump
+SN_RISCV_MC        ?= $(SN_LLVM_BINROOT)/llvm-mc
+SN_RISCV_ADDR2LINE ?= $(SN_LLVM_BINROOT)/llvm-addr2line
 
 # Compiler flags
-SN_MCPU ?= snitch
-SN_RISCV_CFLAGS := -mcpu=$(SN_MCPU)
+SN_RISCV_FEATURES = xfrep xssr xdma xcopift xsmallfloat
+SN_RISCV_CFLAGS := -march=rv32imafd_zfh_zifencei
+SN_RISCV_CFLAGS += $(foreach feat,$(SN_RISCV_FEATURES),-Xclang -target-feature -Xclang +$(feat))
 SN_RISCV_CFLAGS += -menable-experimental-extensions
 SN_RISCV_CFLAGS += -mabi=ilp32d
 SN_RISCV_CFLAGS += -mcmodel=medany
-SN_RISCV_CFLAGS += -mno-fdiv
+# SN_RISCV_CFLAGS += -mno-fdiv
 SN_RISCV_CFLAGS += -fno-builtin-printf
 SN_RISCV_CFLAGS += -fno-builtin-sqrtf
 SN_RISCV_CFLAGS += -fno-common
@@ -49,5 +62,7 @@ SN_RISCV_LDFLAGS += -lm
 SN_RISCV_ARFLAGS := rcs
 
 # Objdump flags
-SN_RISCV_OBJDUMP_FLAGS := --mcpu=$(SN_MCPU)
-SN_RISCV_OBJDUMP_FLAGS += -D
+SN_RISCV_MATTR_FEATURES  = $(call comma-join,$(addprefix +,$(SN_RISCV_FEATURES)))
+SN_RISCV_MATTR_FLAG      = --mattr=+m,+a,+f,+d,+zfh,+zifencei,$(SN_RISCV_MATTR_FEATURES)
+SN_RISCV_OBJDUMP_FLAGS  := --triple=riscv32 $(SN_RISCV_MATTR_FLAG)
+SN_RISCV_OBJDUMP_FLAGS  += -D

util/trace/gen_trace.py

@@ -365,7 +365,7 @@ def load_opcodes():
 
 
 @lru_cache
-def disasm_inst(hex_inst, mc_exec='llvm-mc', mc_flags='-disassemble -mcpu=snitch'):
+def disasm_inst(hex_inst, mc_exec='llvm-mc', mc_flags='-disassemble'):
     """Disassemble a single RISC-V instruction using llvm-mc."""
     # Reverse the endianness of the hex instruction
     inst_fmt = ' '.join(f'0x{byte:02x}' for byte in bytes.fromhex(hex_inst)[::-1])
@@ -1266,7 +1266,7 @@ def main():
     )
     parser.add_argument(
         '--mc-flags',
-        default='-disassemble -mcpu=snitch',
+        default='-disassemble',
         help='Flags to pass to the llvm-mc executable'
     )