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collucacolluca
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hw: Derive TCDM types from UserWidth not user_t
1 parent fb988dd commit 6e31428

17 files changed

Lines changed: 78 additions & 82 deletions

‎hw/snitch_cluster/src/snitch_cc.sv‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@ module snitch_cc #(
1717
parameter int unsigned AddrWidth = 0,
1818
/// Data width of the buses.
1919
parameter int unsigned DataWidth = 0,
20+
/// User width of the TCDM bus.
21+
parameter int unsigned TcdmUserWidth = 0,
2022
/// Data width of the AXI DMA buses.
2123
parameter int unsigned DMADataWidth = 0,
2224
/// Id width of the AXI DMA bus.
@@ -36,8 +38,6 @@ module snitch_cc #(
3638
parameter type tcdm_req_t = logic,
3739
/// Data port response type.
3840
parameter type tcdm_rsp_t = logic,
39-
/// TCDM User Payload
40-
parameter type tcdm_user_t = logic,
4141
parameter type axi_ar_chan_t = logic,
4242
parameter type axi_aw_chan_t = logic,
4343
parameter type axi_req_t = logic,
@@ -763,9 +763,9 @@ module snitch_cc #(
763763
.SsrRegs (SsrRegs),
764764
.AddrWidth (TCDMAddrWidth),
765765
.DataWidth (DataWidth),
766+
.UserWidth (TcdmUserWidth),
766767
.tcdm_req_t (tcdm_req_t),
767-
.tcdm_rsp_t (tcdm_rsp_t),
768-
.tcdm_user_t (tcdm_user_t)
768+
.tcdm_rsp_t (tcdm_rsp_t)
769769
) i_snitch_ssr_streamer (
770770
.clk_i,
771771
.rst_ni ( rst_ni ),
@@ -804,11 +804,10 @@ module snitch_cc #(
804804
.NrPorts (2),
805805
.AddrWidth (TCDMAddrWidth),
806806
.DataWidth (DataWidth),
807+
.UserWidth (TcdmUserWidth),
807808
.RespDepth (SsrMuxRespDepth),
808-
// TODO(zarubaf): USer type
809809
.tcdm_req_t (tcdm_req_t),
810-
.tcdm_rsp_t (tcdm_rsp_t),
811-
.user_t (tcdm_user_t)
810+
.tcdm_rsp_t (tcdm_rsp_t)
812811
) i_tcdm_mux (
813812
.clk_i,
814813
.rst_ni,

‎hw/snitch_cluster/src/snitch_cluster.sv‎

Lines changed: 13 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -218,9 +218,9 @@ module snitch_cluster
218218
/// Derived parameters
219219
localparam int unsigned TCDMSize = NrBanks * TCDMDepth * (NarrowDataWidth/8),
220220
localparam int unsigned TCDMAddrWidth = $clog2(TCDMSize),
221-
localparam type dca_req_t = `DCA_REQ_STRUCT(DataWidth),
222-
localparam type dca_rsp_t = `DCA_RSP_STRUCT(DataWidth)
223-
localparam type tcdm_dma_req_t = `TCDM_REQ_STRUCT(WideDataWidth, TCDMAddrWidth, logic),
221+
localparam type dca_req_t = `DCA_REQ_STRUCT(DcaDataWidth),
222+
localparam type dca_rsp_t = `DCA_RSP_STRUCT(DcaDataWidth),
223+
localparam type tcdm_dma_req_t = `TCDM_REQ_STRUCT(WideDataWidth, TCDMAddrWidth, 1),
224224
localparam type tcdm_dma_rsp_t = `TCDM_RSP_STRUCT(WideDataWidth)
225225
) (
226226
/// System clock. If `IsoCrossing` is enabled this port is the _fast_ clock.
@@ -319,6 +319,11 @@ module snitch_cluster
319319
localparam int unsigned NrSuperBanks = NrBanks / BanksPerSuperBank;
320320
localparam int unsigned DcaLaneDataWidth = NarrowDataWidth;
321321

322+
// tcdm_user_t contains the following fields:
323+
// [CoreIDWidth:1] core_id
324+
// [0:0] is_core
325+
localparam int unsigned TcdmUserWidth = CoreIDWidth + 1;
326+
322327
function automatic int unsigned get_tcdm_ports(int unsigned core);
323328
return (NumSsrs[core] > 1 ? NumSsrs[core] : 1);
324329
endfunction
@@ -464,12 +469,7 @@ module snitch_cluster
464469
typedef logic [CollectiveWidth-1:0] collective_op_t;
465470
typedef logic [AtomicIdWidth-1:0] atomic_id_t;
466471

467-
// Struct replaced by logic array to workaround Questa optimization bug.
468-
// typedef struct packed {
469-
// logic [CoreIDWidth-1:0] core_id;
470-
// bit is_core;
471-
// } tcdm_user_t;
472-
typedef logic [CoreIDWidth:0] tcdm_user_t;
472+
typedef logic [TcdmUserWidth-1:0] tcdm_user_t;
473473

474474
// Regbus peripherals.
475475
`AXI_TYPEDEF_ALL(axi_mst, addr_t, id_mst_t, data_t, strb_t, snitch_cluster_pkg::user_narrow_t)
@@ -490,7 +490,7 @@ module snitch_cluster
490490
`MEM_TYPEDEF_ALL(mem, tcdm_mem_addr_t, data_t, strb_t, tcdm_user_t)
491491
`MEM_TYPEDEF_ALL(mem_dma, tcdm_mem_addr_t, data_dma_t, strb_dma_t, logic)
492492

493-
`TCDM_TYPEDEF_ALL(tcdm, NarrowDataWidth, TCDMAddrWidth, tcdm_user_t)
493+
`TCDM_TYPEDEF_ALL(tcdm, NarrowDataWidth, TCDMAddrWidth, TcdmUserWidth)
494494

495495
// Define dca_lane_req_t and dca_lane_rsp_t
496496
`DCA_TYPEDEF_ALL(dca_lane, DcaLaneDataWidth)
@@ -824,7 +824,6 @@ module snitch_cluster
824824
.NumHyperBanks (NrHyperBanks),
825825
.mem_req_t (mem_dma_req_t),
826826
.mem_rsp_t (mem_dma_rsp_t),
827-
.user_t (logic),
828827
.TcdmAddrWidth (TCDMAddrWidth),
829828
.MemAddrWidth (TCDMMemAddrWidth),
830829
.DataWidth (WideDataWidth),
@@ -844,7 +843,6 @@ module snitch_cluster
844843
.NumHyperBanks (NrHyperBanks),
845844
.mem_req_t (mem_dma_req_t),
846845
.mem_rsp_t (mem_dma_rsp_t),
847-
.user_t (logic),
848846
.TcdmAddrWidth (TCDMAddrWidth),
849847
.MemAddrWidth (TCDMMemAddrWidth),
850848
.DataWidth (WideDataWidth),
@@ -962,7 +960,7 @@ module snitch_cluster
962960
.TcdmAddrWidth (TCDMAddrWidth),
963961
.MemAddrWidth (TCDMMemAddrWidth),
964962
.DataWidth (NarrowDataWidth),
965-
.user_t (tcdm_user_t),
963+
.UserWidth (TcdmUserWidth),
966964
.MemoryResponseLatency (1 + RegisterTCDMCuts),
967965
.Radix (Radix),
968966
.Topology (Topology),
@@ -1047,6 +1045,7 @@ module snitch_cluster
10471045
snitch_cc #(
10481046
.AddrWidth (PhysicalAddrWidth),
10491047
.DataWidth (NarrowDataWidth),
1048+
.TcdmUserWidth (TcdmUserWidth),
10501049
.DMADataWidth (WideDataWidth),
10511050
.DMAIdWidth (WideIdWidthIn),
10521051
.DMAUserWidth (WideUserWidth),
@@ -1058,7 +1057,6 @@ module snitch_cluster
10581057
.drsp_t (reqrsp_rsp_t),
10591058
.tcdm_req_t (tcdm_req_t),
10601059
.tcdm_rsp_t (tcdm_rsp_t),
1061-
.tcdm_user_t (tcdm_user_t),
10621060
.axi_ar_chan_t (axi_mst_dma_ar_chan_t),
10631061
.axi_aw_chan_t (axi_mst_dma_aw_chan_t),
10641062
.axi_req_t (axi_mst_dma_req_t),
@@ -1473,8 +1471,7 @@ module snitch_cluster
14731471
.AddrWidth (PhysicalAddrWidth),
14741472
.DataWidth (NarrowDataWidth),
14751473
.IdWidth (NarrowIdWidthOut),
1476-
// TODO(colluca): this is fragile as it depends on the tcdm_user_t definition
1477-
.UserWidth (CoreIDWidth + 1),
1474+
.UserWidth (TcdmUserWidth),
14781475
.BufDepth (MemoryMacroLatency + 1)
14791476
) i_axi_to_tcdm (
14801477
.clk_i,

‎hw/snitch_cluster/src/snitch_cluster_pkg.sv.tpl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,7 @@ package ${cfg['cluster']['name']}_pkg;
135135
`AXI_TYPEDEF_ALL(wide_in, addr_t, wide_in_id_t, data_dma_t, strb_dma_t, user_dma_t)
136136
`AXI_TYPEDEF_ALL(wide_out, addr_t, wide_out_id_t, data_dma_t, strb_dma_t, user_dma_t)
137137

138-
`TCDM_TYPEDEF_ALL(tcdm_dma, WideDataWidth, TcdmAddrWidth, logic)
138+
`TCDM_TYPEDEF_ALL(tcdm_dma, WideDataWidth, TcdmAddrWidth, 1)
139139
140140
function automatic snitch_pma_pkg::rule_t [snitch_pma_pkg::NrMaxRules-1:0] get_cached_regions();
141141
automatic snitch_pma_pkg::rule_t [snitch_pma_pkg::NrMaxRules-1:0] cached_regions;

‎hw/snitch_cluster/src/snitch_tcdm_fc_interconnect.sv‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,11 +22,11 @@ Parameters:
2222
NumSwitchNets - Number of parallel networks for switch-based interconnects.
2323
SwitchLfsrArbiter - Whether to use an LFSR to arbitrate switch-based networks.
2424
DataWidth - Size of the data payload on the interconnect.
25+
UserWidth - Width of the user field on the interconnect.
2526
TcdmAddrWidth - Address width on the request side.
2627
MemAddrWidth - Address width on the memory side.
2728
MemoryResponseLatency - Latency of memory response (in cycles).
2829
Topology - Interconnect topology.
29-
user_t - Additional user payload to route.
3030
mem_req_t - Type of the data request ports.
3131
mem_rsp_t - Type of the data response ports.
3232
@@ -45,16 +45,16 @@ module snitch_tcdm_fc_interconnect #(
4545
parameter int unsigned NumSwitchNets = 32'd2,
4646
parameter bit SwitchLfsrArbiter = 1'b0,
4747
parameter int unsigned DataWidth = 32,
48+
parameter int unsigned UserWidth = 1,
4849
parameter int unsigned TcdmAddrWidth = 32,
4950
parameter int unsigned MemAddrWidth = 32,
5051
parameter int unsigned MemoryResponseLatency = 1,
5152
parameter snitch_pkg::topo_e Topology = snitch_pkg::LogarithmicInterconnect,
52-
parameter type user_t = logic,
5353
parameter type mem_req_t = logic,
5454
parameter type mem_rsp_t = logic,
5555

5656
// Derived parameters
57-
localparam type tcdm_req_t = `TCDM_REQ_STRUCT(DataWidth, TcdmAddrWidth, user_t),
57+
localparam type tcdm_req_t = `TCDM_REQ_STRUCT(DataWidth, TcdmAddrWidth, UserWidth),
5858
localparam type tcdm_rsp_t = `TCDM_RSP_STRUCT(DataWidth)
5959
) (
6060
input logic clk_i,
@@ -70,6 +70,7 @@ module snitch_tcdm_fc_interconnect #(
7070
typedef logic [MemAddrWidth-1:0] addr_t;
7171
typedef logic [DataWidth-1:0] data_t;
7272
typedef logic [StrbWidth-1:0] strb_t;
73+
typedef logic [UserWidth-1:0] user_t;
7374
`MEM_TYPEDEF_REQ_CHAN_T(mem_req_chan_t, addr_t, data_t, strb_t, user_t);
7475

7576
// Do not assert unconditional stability on write data inside interconnects,

‎hw/snitch_cluster/src/snitch_tcdm_interconnect.sv‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22,11 +22,11 @@ Parameters:
2222
NumSwitchNets - Number of parallel networks for switch-based interconnects.
2323
SwitchLfsrArbiter - Whether to use an LFSR to arbitrate switch-based networks.
2424
DataWidth - Size of the data payload on the interconnect.
25+
UserWidth - Width of the user field on the interconnect.
2526
TcdmAddrWidth - Address width on the request side.
2627
MemAddrWidth - Address width on the memory side.
2728
MemoryResponseLatency - Latency of memory response (in cycles).
2829
Topology - Interconnect topology.
29-
user_t - Additional user payload to route.
3030
mem_req_t - Type of the data request ports.
3131
mem_rsp_t - Type of the data response ports.
3232
@@ -46,15 +46,15 @@ module snitch_tcdm_interconnect #(
4646
parameter int unsigned NumSwitchNets = 32'd2,
4747
parameter bit SwitchLfsrArbiter = 1'b0,
4848
parameter int unsigned DataWidth = 32,
49+
parameter int unsigned UserWidth = 1,
4950
parameter int unsigned TcdmAddrWidth = 32,
5051
parameter int unsigned MemAddrWidth = 32,
5152
parameter int unsigned MemoryResponseLatency = 1,
5253
parameter snitch_pkg::topo_e Topology = snitch_pkg::LogarithmicInterconnect,
53-
parameter type user_t = logic,
5454
parameter type mem_req_t = logic,
5555
parameter type mem_rsp_t = logic,
5656
// Derived parameters
57-
localparam type tcdm_req_t = `TCDM_REQ_STRUCT(DataWidth, TcdmAddrWidth, user_t),
57+
localparam type tcdm_req_t = `TCDM_REQ_STRUCT(DataWidth, TcdmAddrWidth, UserWidth),
5858
localparam type tcdm_rsp_t = `TCDM_RSP_STRUCT(DataWidth)
5959
) (
6060
input logic clk_i,
@@ -72,6 +72,7 @@ module snitch_tcdm_interconnect #(
7272
typedef logic [VirtualMemAddrWidth-1:0] virtual_mem_addr_t;
7373
typedef logic [DataWidth-1:0] data_t;
7474
typedef logic [StrbWidth-1:0] strb_t;
75+
typedef logic [UserWidth-1:0] user_t;
7576

7677
// Define a new datatype to support larger addresses from TCDM interconnect
7778
// We basically pretend to the IC that our banks are combined as larger hyperbanks (Add memoryspace from two banks into one), such that we can demux the address later
@@ -142,7 +143,7 @@ module snitch_tcdm_interconnect #(
142143
.TcdmAddrWidth (TcdmAddrWidth),
143144
.MemAddrWidth (VirtualMemAddrWidth),
144145
.DataWidth (DataWidth),
145-
.user_t (user_t),
146+
.UserWidth (UserWidth),
146147
.MemoryResponseLatency (MemoryResponseLatency),
147148
.Radix (Radix),
148149
.Topology (Topology),

‎hw/snitch_cluster/test/snitch_tcdm_interconnect_tb.sv‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@ module snitch_tcdm_interconnect_tb #(
2020
localparam int unsigned AddrWidth = 32;
2121
localparam int unsigned MemAddrWidth = 15;
2222
localparam int unsigned DataWidth = 32;
23+
localparam int unsigned UserWidth = 1;
2324
localparam int unsigned RespLatency = 1;
2425

2526
localparam int unsigned ByteOffset = $clog2(DataWidth/8);
@@ -29,11 +30,11 @@ module snitch_tcdm_interconnect_tb #(
2930
typedef logic [MemAddrWidth-1:0] tcdm_addr_t;
3031
typedef logic [DataWidth-1:0] data_t;
3132
typedef logic [DataWidth/8-1:0] strb_t;
32-
typedef logic user_t;
33+
typedef logic [UserWidth-1:0] user_t;
3334

3435
logic clk, rst_n;
3536

36-
`TCDM_TYPEDEF_ALL(tcdm, DataWidth, AddrWidth, user_t)
37+
`TCDM_TYPEDEF_ALL(tcdm, DataWidth, AddrWidth, UserWidth)
3738
`MEM_TYPEDEF_ALL(mem, tcdm_addr_t, data_t, strb_t, user_t)
3839

3940
tcdm_req_t [NrInput-1:0] tcdm_req;
@@ -63,14 +64,14 @@ module snitch_tcdm_interconnect_tb #(
6364
TCDM_BUS_DV #(
6465
.ADDR_WIDTH ( AddrWidth ),
6566
.DATA_WIDTH ( DataWidth ),
66-
.user_t (logic)
67+
.user_t ( user_t )
6768
) master_dv [NrInput-1:0](clk);
6869

6970

7071
MEM_BUS_DV #(
7172
.ADDR_WIDTH ( MemAddrWidth ),
7273
.DATA_WIDTH ( DataWidth ),
73-
.user_t (logic)
74+
.user_t ( user_t )
7475
) slave_dv [NrOutput-1:0](clk);
7576

7677
for (genvar i = 0; i < NrInput; i++) begin : gen_input_assign

‎hw/snitch_fp_ss/src/snitch_fp_ss.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ module snitch_fp_ss import snitch_pkg::*; #(
3333
localparam type addr_t = logic [AddrWidth-1:0],
3434
localparam type data_t = logic [DataWidth-1:0],
3535
localparam type dca_req_t = `DCA_REQ_STRUCT(DataWidth),
36-
localparam type dca_rsp_t = `DCA_RSP_STRUCT(DataWidth)
36+
localparam type dca_rsp_t = `DCA_RSP_STRUCT(DataWidth),
3737
localparam type acc_req_t = `SNITCH_ACC_REQ_STRUCT(DataWidth, AddrWidth),
3838
localparam type acc_rsp_t = `SNITCH_ACC_RSP_STRUCT(DataWidth)
3939
) (

‎hw/snitch_ssr/src/snitch_ssr.sv‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ module snitch_ssr import snitch_ssr_pkg::*; #(
1111
parameter ssr_cfg_t Cfg = '0,
1212
parameter int unsigned AddrWidth = 0,
1313
parameter int unsigned DataWidth = 0,
14-
parameter type tcdm_user_t = logic,
14+
parameter int unsigned UserWidth = 0,
1515
parameter type tcdm_req_t = logic,
1616
parameter type tcdm_rsp_t = logic,
1717
parameter type isect_slv_req_t = logic,
@@ -80,7 +80,6 @@ module snitch_ssr import snitch_ssr_pkg::*; #(
8080
.DataWidth ( DataWidth ),
8181
.tcdm_req_t ( tcdm_req_t ),
8282
.tcdm_rsp_t ( tcdm_rsp_t ),
83-
.tcdm_user_t ( tcdm_user_t ),
8483
.isect_slv_req_t ( isect_slv_req_t ),
8584
.isect_slv_rsp_t ( isect_slv_rsp_t ),
8685
.isect_mst_req_t ( isect_mst_req_t ),
@@ -128,7 +127,7 @@ module snitch_ssr import snitch_ssr_pkg::*; #(
128127
.NrPorts ( 2 ),
129128
.AddrWidth ( AddrWidth ),
130129
.DataWidth ( DataWidth ),
131-
.user_t ( tcdm_user_t ),
130+
.UserWidth ( UserWidth ),
132131
.RespDepth ( Cfg.MuxRespDepth ),
133132
.tcdm_req_t ( tcdm_req_t ),
134133
.tcdm_rsp_t ( tcdm_rsp_t )

‎hw/snitch_ssr/src/snitch_ssr_addr_gen.sv‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@ module snitch_ssr_addr_gen import snitch_ssr_pkg::*; #(
1414
parameter int unsigned DataWidth = 0,
1515
parameter type tcdm_req_t = logic,
1616
parameter type tcdm_rsp_t = logic,
17-
parameter type tcdm_user_t = logic,
1817
parameter type isect_slv_req_t = logic,
1918
parameter type isect_slv_rsp_t = logic,
2019
parameter type isect_mst_req_t = logic,
@@ -193,7 +192,6 @@ module snitch_ssr_addr_gen import snitch_ssr_pkg::*; #(
193192
.DataWidth ( DataWidth ),
194193
.tcdm_req_t ( tcdm_req_t ),
195194
.tcdm_rsp_t ( tcdm_rsp_t ),
196-
.tcdm_user_t ( tcdm_user_t ),
197195
.isect_slv_req_t ( isect_slv_req_t ),
198196
.isect_slv_rsp_t ( isect_slv_rsp_t ),
199197
.isect_mst_req_t ( isect_mst_req_t ),

‎hw/snitch_ssr/src/snitch_ssr_indirector.sv‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@ module snitch_ssr_indirector import snitch_ssr_pkg::*; #(
1515
parameter int unsigned DataWidth = 0,
1616
parameter type tcdm_req_t = logic,
1717
parameter type tcdm_rsp_t = logic,
18-
parameter type tcdm_user_t = logic,
1918
parameter type isect_slv_req_t = logic,
2019
parameter type isect_slv_rsp_t = logic,
2120
parameter type isect_mst_req_t = logic,

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