treewide: Add Spyglass flow and fix reported violations (#313)

- Add Spyglass lint flow and bump nonfree repo
- Fix all Spyglass lint errors and warnings
  - Remove redundant $signed conversions
  - Protect against negative array bounds when using default parameter values
  - Derive dependent type parameters
- Fix bug in hive's PTW request connections
- Make `snitch_cluster_pkg.sv` a required source of the cluster, no longer required only by the cluster wrapper and test harness
- Bump OSEDA version to 2026.02 to include Verilator fix verilator/verilator#6824
- Add nonfree `pysynthutils` Python package dependency
- Add Spyglass lint checks (based on pysynthutils) to Gitlab CI
- Increase Yosys synthesis timeout to 3h in Gitlab CI

Author: colluca

.github/actions/setup-python/action.yml

@@ -25,4 +25,4 @@ runs:
     - name: Sync Python environment
       shell: sh
       run: |
-        uv sync --all-extras --locked
+        uv sync --extra all --locked

.gitlab-ci.yml

@@ -73,6 +73,7 @@ snitch-ip-tests:
           - snitch_ssr
           - reqrsp_interface
   script:
+    - make rtl -j
     - cd hw/$IP
     - ./util/compile.sh
     - ./util/run_vsim.sh
@@ -176,7 +177,7 @@ snitch-cluster-copift-sc-vsim:
 ###################################
 
 yosys-synthesis:
-  timeout: 2h
+  timeout: 4h
   script:
     - make CFG_OVERRIDE=cfg/yosys-ci.json yosys
     # Following steps are not included in open-source CI since netlist
@@ -185,11 +186,20 @@ yosys-synthesis:
     - make sw -j
     - make vsim-run SN_BINARY=$PWD/sw/tests/build/simple.elf
 
-################################
-# Non-free implementation flow #
-################################
+#################
+# Non-free jobs #
+#################
 
-nonfree:
+# Non-free elaboration flow
+elab:
   script:
     - make nonfree
     - make elab
+
+# Spyglass lint
+spyglass:
+  script:
+    - make nonfree
+    - make spyglass
+    - util/lint/check_spyglass_lint.py --threshold 3
+        nonfree/lint/build/sg_projects/snitch_cluster/snitch_cluster/lint/lint_rtl/spyglass_reports/moresimple.rpt

Bender.yml

@@ -171,6 +171,7 @@ sources:
   # snitch_cluster
   - files:
       # Level 0
+      - hw/generated/snitch_cluster_pkg.sv
       - hw/snitch_cluster/src/snitch_amo_shim.sv
       - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv
       - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv
@@ -200,9 +201,6 @@ sources:
       - target/sim/tb/tb_bin.sv
 
   # target/snitch_cluster
-  - target: snitch_cluster_wrapper
-    files:
-      - hw/generated/snitch_cluster_pkg.sv
   - target: all(snitch_cluster_wrapper, not(netlist))
     files:
       - hw/generated/snitch_cluster_wrapper.sv

Makefile

@@ -141,7 +141,7 @@ clean-rtl: sn-clean-rtl
 ############
 
 NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/snitch-cluster-nonfree.git
-NONFREE_COMMIT ?= 45ffdbd53f04cafbcd8369bbcaf04b3ee8a90b31
+NONFREE_COMMIT ?= 3da8864984e3dafbc63ce5de13f5e1fdaa135ac7
 NONFREE_DIR = $(SN_ROOT)/nonfree
 
 .PHONY: nonfree clean-nonfree

hw/reqrsp_interface/src/reqrsp_iso.sv

@@ -45,7 +45,7 @@ module reqrsp_iso #(
   typedef logic [AddrWidth-1:0] addr_t;
   typedef logic [DataWidth-1:0] data_t;
   typedef logic [DataWidth/8-1:0] strb_t;
-  typedef logic [UserWidth-1:0] user_t;
+  typedef logic [cf_math_pkg::iomsb(UserWidth):0] user_t;
 
   `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)
 
@@ -115,7 +115,7 @@ module reqrsp_iso_intf #(
   typedef logic [AddrWidth-1:0] addr_t;
   typedef logic [DataWidth-1:0] data_t;
   typedef logic [DataWidth/8-1:0] strb_t;
-  typedef logic [UserWidth-1:0] user_t;
+  typedef logic [cf_math_pkg::iomsb(UserWidth):0] user_t;
 
   `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)
 

hw/reqrsp_interface/src/reqrsp_to_axi.sv

@@ -172,7 +172,7 @@ module reqrsp_to_axi import reqrsp_pkg::*; import snitch_pkg::*; #(
   assign axi_req_o.ar.burst  = axi_pkg::BURST_INCR;
   assign axi_req_o.ar.lock   = (reqrsp_req_i.q.amo == AMOLR);
   assign axi_req_o.ar.cache  = axi_pkg::CACHE_MODIFIABLE;
-  assign axi_req_o.ar.id     = $unsigned(ID);
+  assign axi_req_o.ar.id     = ID;
   assign axi_req_o.ar.user   = reqrsp_req_i.q.user;
   assign axi_req_o.ar_valid  = q_valid_read;
   assign q_ready_read        = axi_rsp_i.ar_ready;
@@ -187,7 +187,7 @@ module reqrsp_to_axi import reqrsp_pkg::*; import snitch_pkg::*; #(
   assign axi_req_o.aw.burst  = axi_pkg::BURST_INCR;
   assign axi_req_o.aw.lock   = (reqrsp_req_i.q.amo == AMOSC);
   assign axi_req_o.aw.cache  = axi_pkg::CACHE_MODIFIABLE;
-  assign axi_req_o.aw.id     = $unsigned(ID);
+  assign axi_req_o.aw.id     = ID;
   assign axi_req_o.aw.user   = reqrsp_req_i.q.user;
   assign axi_req_o.w.data    = write_data;
   assign axi_req_o.w.strb    = reqrsp_req_i.q.strb;

hw/snitch/src/snitch.sv

@@ -3605,13 +3605,13 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
         alu_result = {30'b0, ~adder_result[32]};
       end
       Sltu: begin
-        alu_opa = $unsigned(opa);
-        alu_opb = -$unsigned(opb);
+        alu_opa = opa;
+        alu_opb = -opb;
         alu_result = {30'b0, adder_result[32]};
       end
       Geu: begin
-        alu_opa = $unsigned(opa);
-        alu_opb = -$unsigned(opb);
+        alu_opa = opa;
+        alu_opb = -opb;
         alu_result = {30'b0, ~adder_result[32]};
       end
       Sll: begin
@@ -3683,8 +3683,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
     assign ptw_req_o[1].va    = '0;
   end
 
-  assign ptw_req_o[0].ppn = $unsigned(satp_q.ppn);
-  assign ptw_req_o[1].ppn = $unsigned(satp_q.ppn);
+  assign ptw_req_o[0].ppn = satp_q.ppn;
+  assign ptw_req_o[1].ppn = satp_q.ppn;
 
   // Translation is active if it is set in SATP and we are not in machine mode or debug mode.
   assign trans_active = satp_q.mode & (priv_lvl_q != PrivLvlM) & ~debug_q;
@@ -3710,7 +3710,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
   // --------------------
   data_t lsu_qdata;
   // sign exten to appropriate length
-  assign lsu_qdata = $unsigned((ls_amo == AMONone) ? opc : opb);
+  assign lsu_qdata = (ls_amo == AMONone) ? opc : opb;
 
   // Consider CAQ in accelerator handshake when offloading an FPU load or store.
   assign caq_ena = is_fp_load | is_fp_store;

hw/snitch/src/snitch_l0_tlb.sv

@@ -55,22 +55,22 @@ module snitch_l0_tlb import snitch_pkg::*; #(
     /// This is a 4 mega page entry.
     logic is_4mega;
   } tag_t;
-  tag_t [NrEntries-1:0] tag_d, tag_q;
-  logic [NrEntries-1:0] is_4mega_exp; //expanded version
+  tag_t [cf_math_pkg::iomsb(NrEntries):0] tag_d, tag_q;
+  logic [cf_math_pkg::iomsb(NrEntries):0] is_4mega_exp; //expanded version
   logic is_4mega;
   // Tag is valid array.
-  logic [NrEntries-1:0] tag_valid_d, tag_valid_q;
+  logic [cf_math_pkg::iomsb(NrEntries):0] tag_valid_d, tag_valid_q;
   logic [$clog2(NrEntries+1)-1:0] evict_d, evict_q;
 
-  l0_pte_t [NrEntries-1:0] pte_q, pte_d;
+  l0_pte_t [cf_math_pkg::iomsb(NrEntries):0] pte_q, pte_d;
 
   l0_pte_t pte;
 
   `FFAR(tag_valid_q, tag_valid_d, '0, clk_i, rst_i)
   `FFAR(tag_q, tag_d, '0, clk_i, rst_i)
   `FFAR(pte_q, pte_d, '0, clk_i, rst_i)
 
-  logic [NrEntries-1:0] hit;
+  logic [cf_math_pkg::iomsb(NrEntries):0] hit;
   logic miss_d, miss_q; // we got a miss
   logic refill_d, refill_q; // refill request is underway
 

hw/snitch/src/snitch_lsu.sv

@@ -273,7 +273,7 @@ module snitch_lsu import cf_math_pkg::*; #(
 
   // Re-align write data.
   /* verilator lint_off WIDTH */
-  assign lsu_qdata = $unsigned(lsu_qdata_i);
+  assign lsu_qdata = lsu_qdata_i;
   always_comb begin
     unique case (lsu_qaddr_i[DataAlign-1:0])
       3'b000: data_qdata = lsu_qdata;

hw/snitch_cluster/src/snitch_amo_shim.sv

@@ -186,7 +186,7 @@ module snitch_amo_shim
   // Atomics
   // -------
   logic [63:0] wdata;
-  assign wdata = $unsigned(wdata_i);
+  assign wdata = wdata_i;
 
   `FF(state_q, state_d, Idle)
   `FFL(amo_op_q, amo_i, load_amo, AMONone, clk_i, rst_ni)
@@ -295,13 +295,13 @@ module snitch_amo_alu import snitch_pkg::*; (
                 result_o = adder_sum[32] ? operand_a_i : operand_b_i;
             end
             AMOMaxu: begin
-                adder_operand_a = $unsigned(operand_a_i);
-                adder_operand_b = -$unsigned(operand_b_i);
+                adder_operand_a = operand_a_i;
+                adder_operand_b = -operand_b_i;
                 result_o = adder_sum[32] ? operand_b_i : operand_a_i;
             end
             AMOMinu: begin
-                adder_operand_a = $unsigned(operand_a_i);
-                adder_operand_b = -$unsigned(operand_b_i);
+                adder_operand_a = operand_a_i;
+                adder_operand_b = -operand_b_i;
                 result_o = adder_sum[32] ? operand_a_i : operand_b_i;
             end
             default: result_o = '0;