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treewide: Bump riscv-opcodes after merge with upstream #316

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treewide: Bump riscv-opcodes after merge with upstream #316

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2b237b3
hw: Always offload unsupported instructions to CV-X-IF
colluca May 1, 2026
079e618
treewide: Bump riscv-opcodes after merge with upstream
colluca May 4, 2026
f9bc852
util/clustergen: Move opcodes to separate file
colluca Apr 30, 2026
c36a44e
sw: Remove dma intrinsics and dmcpyi instructions
colluca Apr 30, 2026
9555be5
sw: Update code for LLVM 18
colluca May 2, 2026
0f889cb
sw: Remove all use of custom compiler intrinsics
colluca May 2, 2026
ec05465
treewide: Update toolchain flags for minimal, auto-generated toolchain
colluca Apr 30, 2026
4a9c422
cfg: Enable divsqrt until -mno-fdiv is restored in new toolchain
colluca May 5, 2026
d1319d4
hw: Change FREP encoding to not require imm12m1 in toolchain
colluca May 5, 2026
e266556
Bump cluster_icache with L0 bug fix
colluca May 6, 2026
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4 changes: 2 additions & 2 deletions Bender.lock
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Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,8 @@ packages:
dependencies:
- common_cells
cluster_icache:
revision: 1642961b9561513f283674efc2c90f24855e8d39
version: 0.3.1
revision: 12bf7d077ff1d1e4d450bd3afc0f12a927e21a20
version: null
source:
Git: https://github.com/pulp-platform/cluster_icache.git
dependencies:
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6 changes: 6 additions & 0 deletions REUSE.toml
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Expand Up @@ -85,3 +85,9 @@ SPDX-License-Identifier = "Apache-2.0"
path = "sw/runtime/src/omp/interface.h"
SPDX-FileCopyrightText = "LLVM Project"
SPDX-License-Identifier = "Apache-2.0 WITH LLVM-exception"

# Lists
[[annotations]]
path = ["util/clustergen/opcodes.txt"]
SPDX-FileCopyrightText = "2020 ETH Zurich and University of Bologna"
SPDX-License-Identifier = "Apache-2.0"
1 change: 1 addition & 0 deletions cfg/default.json
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Expand Up @@ -94,6 +94,7 @@
// Templates.
compute_core_template: {
isa: "rv32imafd",
Xdiv_sqrt: true,
xssr: true,
xfrep: true,
xcopift: true,
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1 change: 1 addition & 0 deletions cfg/github-ci.json
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Expand Up @@ -90,6 +90,7 @@
// Templates.
compute_core_template: {
isa: "rv32imafd",
Xdiv_sqrt: true,
xssr: true,
xfrep: true,
xcopift: true,
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2,544 changes: 1,334 additions & 1,210 deletions hw/snitch/src/riscv_instr.sv
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