treewide: Bump common_cells to v2

Bender.lock

@@ -1,13 +1,13 @@
 packages:
   apb:
-    revision: 77ddf073f194d44b9119949d2421be59789e69ae
-    version: 0.2.4
+    revision: c36e398b5e9b02f3a5fb1511be02764c94e1c413
+    version: null
     source:
       Git: https://github.com/pulp-platform/apb.git
     dependencies:
     - common_cells
   axi:
-    revision: 06410c36819924e32db2afa428d244dbdbcd5d4e
+    revision: 5a15312389ff1f9d48dba03790c14c2f9c86080f
     version: null
     source:
       Git: https://github.com/colluca/axi.git
@@ -16,8 +16,8 @@ packages:
     - common_verification
     - tech_cells_generic
   axi_riscv_atomics:
-    revision: 0ac3a78fe342c5a5b9b10bff49d58897f773059e
-    version: 0.8.2
+    revision: f042b045fc33628eb55c128d8f31ba4db4fdb9f8
+    version: null
     source:
       Git: https://github.com/pulp-platform/axi_riscv_atomics.git
     dependencies:
@@ -32,8 +32,8 @@ packages:
     dependencies:
     - common_cells
   cluster_icache:
-    revision: 1642961b9561513f283674efc2c90f24855e8d39
-    version: 0.3.1
+    revision: 15e492f7064831d1fe12af25460929b16606e4cd
+    version: null
     source:
       Git: https://github.com/pulp-platform/cluster_icache.git
     dependencies:
@@ -42,7 +42,7 @@ packages:
     - scm
     - tech_cells_generic
   common_cells:
-    revision: ca9d577f2fbc45ec557ab4e0905bbfc154441540
+    revision: ab3d6408b7ef5c96ecf2c59fb67d5d3c268173a8
     version: null
     source:
       Git: https://github.com/pulp-platform/common_cells.git
@@ -56,7 +56,7 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   fpnew:
-    revision: e5aa6a01b5bbe1675c3aa8872e1203413ded83d1
+    revision: 0e66ccc7ced8c3c4dd495792d26d81af976eec76
     version: null
     source:
       Git: https://github.com/pulp-platform/cvfpu.git
@@ -71,10 +71,10 @@ packages:
     dependencies:
     - common_cells
   idma:
-    revision: 28a36e5e07705549e59fc33db96ab681bc1ca88e
-    version: 0.6.5
+    revision: 4e908d763c41abbc3c28850e6cb247f5d845a0d6
+    version: null
     source:
-      Git: https://github.com/pulp-platform/iDMA.git
+      Git: https://github.com/pulp-platform/idma.git
     dependencies:
     - axi
     - axi_stream
@@ -83,16 +83,16 @@ packages:
     - obi
     - register_interface
   obi:
-    revision: 0155fc34e900c7c884e081c0a1114a247937ff69
-    version: 0.1.7
+    revision: ddeced68bf1d180750171384eed809628eb890c7
+    version: null
     source:
       Git: https://github.com/pulp-platform/obi.git
     dependencies:
     - common_cells
     - common_verification
   register_interface:
-    revision: d6e1d4cdaab7870f4faf3f88a1c788eaf5ac129d
-    version: 0.4.7
+    revision: f04dc815b72e32ae483b2abafcb87a8f4b6c37e7
+    version: null
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:

Bender.yml

@@ -22,15 +22,15 @@ remotes:
   pulp: https://github.com/pulp-platform
 
 dependencies:
-  axi_riscv_atomics: 0.8.2
-  apb: 0.2.2
   tech_cells_generic: 0.2.13
   riscv-dbg: 0.8.1
-  cluster_icache: 0.3.0
-  idma: 0.6.5
-  axi:                { git: https://github.com/colluca/axi.git,                      rev:      multicast   }
-  common_cells:       { git: https://github.com/pulp-platform/common_cells.git,       rev:      snitch      }
-  FPnew:              { git: https://github.com/pulp-platform/cvfpu.git,              rev:      pulp-v0.2.3 }
+  cluster_icache:    { git: https://github.com/pulp-platform/cluster_icache.git,    rev: common-cells-v2 }
+  axi_riscv_atomics: { git: https://github.com/pulp-platform/axi_riscv_atomics.git, rev: common-cells-v2 }
+  apb:               { git: https://github.com/pulp-platform/apb.git,               rev: common-cells-v2 }
+  idma:              { git: https://github.com/pulp-platform/idma.git,              rev: __deploy__fd58a9f__common-cells-v2 }
+  axi:               { git: https://github.com/colluca/axi.git,                     rev: multicast   }
+  common_cells:      { git: https://github.com/pulp-platform/common_cells.git,      rev: v2-test     }
+  FPnew:             { git: https://github.com/pulp-platform/cvfpu.git,             rev: common-cells-v2 }
 
 export_include_dirs:
   - hw/reqrsp_interface/include

hw/dca_interface/src/dca_fork.sv

@@ -32,7 +32,7 @@ module dca_fork #(
   logic [NumLanes-1:0] flat_p_readies;
 
   // Fork the DCA request to all lanes
-  stream_fork #(
+  cc_stream_fork #(
     .N_OUP(NumLanes)
   ) i_dca_fork_fpu (
     .clk_i  (clk_i),
@@ -44,7 +44,7 @@ module dca_fork #(
   );
 
   // Join the DCA responses from all lanes
-  stream_join #(
+  cc_stream_join #(
     .N_INP(NumLanes)
   ) i_dca_join_fpu (
     .inp_valid_i(flat_p_valids),

hw/reqrsp_interface/src/axi_to_reqrsp.sv

@@ -189,7 +189,7 @@ module axi_to_reqrsp #(
   end
 
   // Arbitrate between reads and writes.
-  stream_mux #(
+  cc_stream_mux #(
     .DATA_T ( meta_t ),
     .N_INP  ( 32'd2  )
   ) i_ax_mux (
@@ -246,7 +246,7 @@ module axi_to_reqrsp #(
   end
 
   // Fork arbitrated stream to meta data, memory requests, and R/B channel selection.
-  stream_fork #(
+  cc_stream_fork #(
     .N_OUP ( 32'd3 )
   ) i_fork (
     .clk_i,
@@ -260,15 +260,14 @@ module axi_to_reqrsp #(
   assign sel_b = meta.write & meta.last;
   assign sel_r = ~meta.write | meta.atop[5];
 
-  stream_fifo #(
+  cc_stream_fifo #(
     .FALL_THROUGH ( 1'b1             ),
     .DEPTH        ( 32'd1 + BufDepth ),
     .T            ( logic[1:0]       )
   ) i_sel_buf (
     .clk_i,
     .rst_ni,
     .flush_i    ( 1'b0                    ),
-    .testmode_i ( 1'b0                    ),
     .data_i     ({sel_b,        sel_r    }),
     .valid_i    ( sel_valid               ),
     .ready_o    ( sel_ready               ),
@@ -278,15 +277,14 @@ module axi_to_reqrsp #(
     .usage_o    ( /* unused */            )
   );
 
-  stream_fifo #(
+  cc_stream_fifo #(
     .FALL_THROUGH ( 1'b1             ),
     .DEPTH        ( 32'd1 + BufDepth ),
     .T            ( meta_t           )
   ) i_meta_buf (
     .clk_i,
     .rst_ni,
     .flush_i    ( 1'b0           ),
-    .testmode_i ( 1'b0           ),
     .data_i     ( meta           ),
     .valid_i    ( meta_valid     ),
     .ready_o    ( meta_ready     ),
@@ -321,7 +319,7 @@ module axi_to_reqrsp #(
 
   // Join memory read data and meta data stream.
   logic mem_join_valid, mem_join_ready;
-  stream_join #(
+  cc_stream_join #(
     .N_INP ( 32'd2 )
   ) i_join (
     .inp_valid_i  ({reqrsp_rsp_i.p_valid, meta_buf_valid}),
@@ -331,7 +329,7 @@ module axi_to_reqrsp #(
   );
 
   // Dynamically fork the joined stream to B and R channels.
-  stream_fork_dynamic #(
+  cc_stream_fork_dynamic #(
     .N_OUP ( 32'd2 )
   ) i_fork_dynamic (
     .clk_i,

hw/reqrsp_interface/src/generic_reqrsp_cut.sv

@@ -28,7 +28,7 @@ module generic_reqrsp_cut #(
     input  rsp_t mst_rsp_i
 );
 
-  spill_register #(
+  cc_spill_register #(
     .T     (req_chan_t),
     .Bypass(BypassReq)
   ) i_spill_register_q (
@@ -42,7 +42,7 @@ module generic_reqrsp_cut #(
     .data_o (mst_req_o.q)
   );
 
-  spill_register #(
+  cc_spill_register #(
     .T     (rsp_chan_t),
     .Bypass(BypassRsp)
   ) i_spill_register_p (

hw/reqrsp_interface/src/generic_reqrsp_demux.sv

@@ -30,7 +30,7 @@ module generic_reqrsp_demux #(
   parameter type         req_chan_t = logic,
   parameter type         rsp_chan_t = logic,
   // Dependent parameters
-  localparam int unsigned IdxWidth = cf_math_pkg::idx_width(NrPorts),
+  localparam int unsigned IdxWidth = cc_pkg::idx_width(NrPorts),
   localparam type         req_t    = `GENERIC_REQRSP_REQ_STRUCT(req_chan_t),
   localparam type         rsp_t    = `GENERIC_REQRSP_RSP_STRUCT(rsp_chan_t)
 ) (
@@ -48,7 +48,7 @@ module generic_reqrsp_demux #(
   rsp_chan_t [NrPorts-1:0] mst_p_data;
 
   // Demux the request valid/ready handshake to the selected master port.
-  stream_demux #(
+  cc_stream_demux #(
     .N_OUP(NrPorts)
   ) i_stream_demux (
     .inp_valid_i(slv_req_i.q_valid),
@@ -59,7 +59,7 @@ module generic_reqrsp_demux #(
   );
 
   // Arbitrate responses from all master ports back to the slave.
-  stream_arbiter #(
+  cc_stream_arbiter #(
     .DATA_T(rsp_chan_t),
     .N_INP (NrPorts)
   ) i_stream_arbiter (

hw/reqrsp_interface/src/generic_reqrsp_mux.sv

@@ -25,7 +25,7 @@ module generic_reqrsp_mux #(
   parameter bit               ExtRspRoute = 1'b0,
   /// Dependent parameters *do not override*
   /// Width of the arbitrated index.
-  localparam int unsigned     IdxWidth    = cf_math_pkg::idx_width(NrPorts),
+  localparam int unsigned     IdxWidth    = cc_pkg::idx_width(NrPorts),
   localparam type             req_t       = `GENERIC_REQRSP_REQ_STRUCT(req_chan_t),
   localparam type             rsp_t       = `GENERIC_REQRSP_RSP_STRUCT(rsp_chan_t)
 ) (
@@ -55,7 +55,7 @@ module generic_reqrsp_mux #(
 
   // Optionally cut the incoming paths
   for (genvar i = 0; i < NrPorts; i++) begin : gen_cuts
-    spill_register #(
+    cc_spill_register #(
       .T (req_chan_t),
       .Bypass (!RegisterReq[i])
     ) i_spill_register_req (
@@ -78,7 +78,7 @@ module generic_reqrsp_mux #(
   end
 
   /// Arbitrate requests
-  rr_arb_tree #(
+  cc_rr_arb_tree #(
     .NumIn (NrPorts),
     .DataType (req_chan_t),
     .AxiVldRdy (1'b1),
@@ -111,21 +111,20 @@ module generic_reqrsp_mux #(
       // For the "normal" case we need to save the arbitration decision. We do so
       // by converting the handshake into a binary signal which we save for
       // response routing.
-      onehot_to_bin #(
+      cc_onehot_to_bin #(
         .ONEHOT_WIDTH (NrPorts)
       ) i_onehot_to_bin (
         .onehot (req_valid_q & req_ready_q),
         .bin    (idx)
       );
       // Save the arbitration decision.
-      fifo_v3 #(
+      cc_fifo #(
         .DATA_WIDTH (IdxWidth),
         .DEPTH (RspDepth)
       ) i_rsp_fifo (
         .clk_i,
         .rst_ni,
         .flush_i (1'b0),
-        .testmode_i (1'b0),
         .full_o (full),
         .empty_o (),
         .usage_o (),

hw/reqrsp_interface/src/reqrsp_demux.sv

@@ -17,7 +17,7 @@ module reqrsp_demux #(
     /// Amount of outstanding responses. Determines the FIFO size.
     parameter int unsigned RespDepth   = 8,
     // Dependent parameters, DO NOT OVERRIDE!
-    parameter int unsigned SelectWidth = cf_math_pkg::idx_width(NrPorts),
+    parameter int unsigned SelectWidth = cc_pkg::idx_width(NrPorts),
     parameter type         select_t    = logic [SelectWidth-1:0]
 ) (
     input  logic               clk_i,
@@ -58,14 +58,13 @@ module reqrsp_demux #(
   end
 
   // Remember selected master for correct forwarding of read data/acknowledge.
-  fifo_v3 #(
+  cc_fifo #(
     .DATA_WIDTH ( NrPorts ),
     .DEPTH ( RespDepth )
   ) i_id_fifo (
     .clk_i,
     .rst_ni,
     .flush_i (1'b0),
-    .testmode_i (1'b0),
     .full_o (fifo_full),
     .empty_o (fifo_empty),
     .usage_o ( ),
@@ -109,7 +108,7 @@ module reqrsp_demux_intf #(
     /// Amount of outstanding responses. Determines the FIFO size.
     parameter int unsigned RespDepth    = 8,
     // Dependent parameters, DO NOT OVERRIDE!
-    parameter int unsigned SelectWidth    = cf_math_pkg::idx_width(NrPorts),
+    parameter int unsigned SelectWidth    = cc_pkg::idx_width(NrPorts),
     parameter type         select_t       = logic [SelectWidth-1:0]
 ) (
     input  logic    clk_i,

hw/reqrsp_interface/src/reqrsp_iso.sv

@@ -45,11 +45,11 @@ module reqrsp_iso #(
   typedef logic [AddrWidth-1:0] addr_t;
   typedef logic [DataWidth-1:0] data_t;
   typedef logic [DataWidth/8-1:0] strb_t;
-  typedef logic [cf_math_pkg::iomsb(UserWidth):0] user_t;
+  typedef logic [cc_pkg::iomsb(UserWidth):0] user_t;
 
   `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)
 
-  isochronous_spill_register #(
+  cc_isochronous_spill_register #(
     .T (reqrsp_req_chan_t),
     .Bypass (BypassReq)
   ) i_isochronous_spill_register_q (
@@ -65,7 +65,7 @@ module reqrsp_iso #(
     .dst_data_o (dst_req_o.q)
   );
 
-  isochronous_spill_register #(
+  cc_isochronous_spill_register #(
     .T (reqrsp_rsp_chan_t),
     .Bypass (BypassRsp)
   ) i_isochronous_spill_register_p (
@@ -115,7 +115,7 @@ module reqrsp_iso_intf #(
   typedef logic [AddrWidth-1:0] addr_t;
   typedef logic [DataWidth-1:0] data_t;
   typedef logic [DataWidth/8-1:0] strb_t;
-  typedef logic [cf_math_pkg::iomsb(UserWidth):0] user_t;
+  typedef logic [cc_pkg::iomsb(UserWidth):0] user_t;
 
   `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)
 

hw/reqrsp_interface/src/reqrsp_to_axi.sv

@@ -61,7 +61,7 @@ module reqrsp_to_axi import reqrsp_pkg::*; import snitch_pkg::*; #(
   input  axi_rsp_t axi_rsp_i
 );
 
-  localparam int unsigned CounterWidth = cf_math_pkg::idx_width(MaxTrans);
+  localparam int unsigned CounterWidth = cc_pkg::idx_width(MaxTrans);
   typedef logic [CounterWidth-1:0] cnt_t;
   logic req_is_amo;
   logic is_write;
@@ -195,7 +195,7 @@ module reqrsp_to_axi import reqrsp_pkg::*; import snitch_pkg::*; #(
   assign axi_req_o.w.user    = reqrsp_req_i.q.user;
 
   // Both channels need to handshake (independently).
-  stream_fork #(
+  cc_stream_fork #(
     .N_OUP (2)
   ) i_stream_fork (
     .clk_i,

hw/reqrsp_interface/test/reqrsp_demux_tb.sv

@@ -22,7 +22,7 @@ module reqrsp_demux_tb import reqrsp_pkg::*; #(
   localparam time ClkPeriod = 10ns;
   localparam time ApplTime =  2ns;
   localparam time TestTime =  8ns;
-  localparam int unsigned SelectWidth = cf_math_pkg::idx_width(NrPorts);
+  localparam int unsigned SelectWidth = cc_pkg::idx_width(NrPorts);
   typedef logic [SelectWidth-1:0] select_t;
   logic  clk, rst_n;
   select_t slv_select;