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rgiuntirgiunti
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[LINT] trailing spaces, unuseful comments
1 parent b92c84d commit 36d78f8

22 files changed

Lines changed: 70 additions & 93 deletions

‎hw/ip/snitch/src/riscv_instr.sv‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1338,5 +1338,4 @@ package riscv_instr;
13381338
localparam logic [11:0] CSR_MHPMCOUNTER29H = 12'hb9d;
13391339
localparam logic [11:0] CSR_MHPMCOUNTER30H = 12'hb9e;
13401340
localparam logic [11:0] CSR_MHPMCOUNTER31H = 12'hb9f;
1341-
13421341
endpackage

‎hw/ip/snitch/src/snitch.sv‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2371,7 +2371,6 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
23712371
riscv_instr::VREDMINU_VS,
23722372
riscv_instr::VREDMAX_VS,
23732373
riscv_instr::VREDMAXU_VS,
2374-
// CMY: add VMANDNOT VMAND VMOR VMXOR VMORNOT VMNAND VMNOR VMXNOR, 8 masking instructions
23752374
riscv_instr::VMANDN_MM,
23762375
riscv_instr::VMAND_MM,
23772376
riscv_instr::VMOR_MM,
@@ -2380,7 +2379,6 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
23802379
riscv_instr::VMNAND_MM,
23812380
riscv_instr::VMNOR_MM,
23822381
riscv_instr::VMXNOR_MM,
2383-
//----------------------------------------------------------
23842382
riscv_instr::VMSEQ_VV,
23852383
riscv_instr::VMSEQ_VI,
23862384
riscv_instr::VMSNE_VV,

‎hw/ip/spatz/src/spatz.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -458,7 +458,7 @@ module spatz import spatz_pkg::*; import rvv_pkg::*; import fpnew_pkg::*; #(
458458
.vfu_rsp_o (vfu_rsp ),
459459
// VRF
460460
.vrf_waddr_o (vrf_waddr[VFU_VD_WD] ),
461-
.vrf_wdata_o (vrf_wdata[VFU_VD_WD] ), // N_FU*ELEN bits
461+
.vrf_wdata_o (vrf_wdata[VFU_VD_WD] ),
462462
.vrf_we_o (sb_we[VFU_VD_WD] ),
463463
.vrf_wbe_o (vrf_wbe[VFU_VD_WD] ),
464464
`ifdef BUF_FPU

‎hw/ip/spatz/src/spatz_controller.sv‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -199,7 +199,7 @@ module spatz_controller
199199
logic req_buffer_ready, req_buffer_valid, req_buffer_pop;
200200

201201
// One element wide instruction buffer
202-
fall_through_register #( // a fifo.
202+
fall_through_register #(
203203
.T(spatz_req_t)
204204
) i_req_buffer (
205205
.clk_i (clk_i ),
@@ -431,12 +431,11 @@ module spatz_controller
431431
scoreboard_d[spatz_req.id].deps[write_table_d[spatz_req.vd].id] |= write_table_d[spatz_req.vd].valid;
432432
read_table_d[spatz_req.vd] = {spatz_req.id, 1'b1};
433433
end
434-
// CMY: tackling v0 RAW hazard-------------------------------------------------------
434+
// tackling v0 RAW hazard
435435
if (!spatz_req.op_arith.vm) begin
436436
scoreboard_d[spatz_req.id].deps[write_table_d[0].id] |= write_table_d[0].valid;
437437
read_table_d[0] = {spatz_req.id, 1'b1};
438438
end
439-
//--------------------------------------------------------------------------------------
440439

441440
// WAW and WAR hazards
442441
if (spatz_req.use_vd) begin
@@ -561,7 +560,7 @@ module spatz_controller
561560
running_insn_d = running_insn_q;
562561

563562
// New instruction!
564-
if (spatz_req_valid && spatz_req.ex_unit != CON) // declare a new instruction
563+
if (spatz_req_valid && spatz_req.ex_unit != CON)
565564
running_insn_d[next_insn_id] = 1'b1;
566565

567566
// Finished a instruction

‎hw/ip/spatz/src/spatz_decoder.sv‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -274,7 +274,6 @@ module spatz_decoder
274274
riscv_instr::VREDMINU_VS,
275275
riscv_instr::VREDMAX_VS,
276276
riscv_instr::VREDMAXU_VS,
277-
// CMY: add VMANDNOT VMAND VMOR VMXOR VMORNOT VMNAND VMNOR VMXNOR, 8 masking instructions
278277
riscv_instr::VMANDN_MM,
279278
riscv_instr::VMAND_MM,
280279
riscv_instr::VMOR_MM,
@@ -283,7 +282,6 @@ module spatz_decoder
283282
riscv_instr::VMNAND_MM,
284283
riscv_instr::VMNOR_MM,
285284
riscv_instr::VMXNOR_MM,
286-
//-------------------------------------------------------------
287285
riscv_instr::VMSEQ_VV,
288286
riscv_instr::VMSEQ_VX,
289287
riscv_instr::VMSEQ_VI,
@@ -358,7 +356,7 @@ module spatz_decoder
358356
automatic vreg_t arith_s1 = decoder_req_i.instr[19:15];
359357
automatic vreg_t arith_s2 = decoder_req_i.instr[24:20];
360358
automatic vreg_t arith_d = decoder_req_i.instr[11:7];
361-
automatic logic arith_vm = decoder_req_i.instr[25]; //Vector Arithmetic Masking Enable bit
359+
automatic logic arith_vm = decoder_req_i.instr[25];
362360

363361
spatz_req.op_arith.vm = arith_vm;
364362
spatz_req.op_sld.vm = arith_vm;
@@ -837,7 +835,6 @@ module spatz_decoder
837835
end
838836
end
839837

840-
// CMY: Mask operations
841838
riscv_instr::VMANDN_MM: begin
842839
spatz_req.op = VMANDNOT;
843840
end

‎hw/ip/spatz/src/spatz_ipu.sv‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -478,7 +478,6 @@ module spatz_ipu import spatz_pkg::*; import rvv_pkg::vew_e; #(
478478
///////////////
479479

480480
// Collect results from the SIMD lanes
481-
// each lane is responsible for calculating one element.
482481
always_comb begin : collector
483482
unique case (sew)
484483
rvv_pkg::EW_8 : begin

‎hw/ip/spatz/src/spatz_pkg.sv.tpl‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -120,10 +120,6 @@ package spatz_pkg;
120120
typedef logic [VFURespAddrWidth-1:0] vfu_rsp_addr_t;
121121
typedef logic [N_FU*ELENB-1:0] vrf_be_t;
122122
typedef logic [N_FU*ELEN-1:0] vrf_data_t;
123-
// ELEN = 64
124-
// The VRF is centralized and serves all functional units.
125-
// Each VRF port is 64F-bit wide. F denotes the number of FPUs.
126-
// the FU here doesn't refer to Functioan Units. N_FU=max{N_IPU,N_FPU}
127123

128124
// Instruction ID
129125
typedef logic [$clog2(NrParallelInstructions)-1:0] spatz_id_t;

‎hw/ip/spatz/src/spatz_simd_lane.sv‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -220,14 +220,14 @@ module spatz_simd_lane import spatz_pkg::*; import rvv_pkg::vew_e; #(
220220
VSUB, VRSUB, VNMSAC, VNMSUB, VSBC: simd_result = subtractor_result[Width-1:0];
221221
VMIN, VMINU : simd_result = $signed({op_s1_i[Width-1] & is_signed_i, op_s1_i}) <= $signed({op_s2_i[Width-1] & is_signed_i, op_s2_i}) ? op_s1_i : op_s2_i;
222222
VMAX, VMAXU : simd_result = $signed({op_s1_i[Width-1] & is_signed_i, op_s1_i}) > $signed({op_s2_i[Width-1] & is_signed_i, op_s2_i}) ? op_s1_i : op_s2_i;
223-
VAND, VMAND : simd_result = op_s1_i & op_s2_i; // CMY: add masking support
224-
VOR , VMOR : simd_result = op_s1_i | op_s2_i; // like above
225-
VXOR, VMXOR : simd_result = op_s1_i ^ op_s2_i; // like above
226-
VMANDNOT : simd_result = ~op_s1_i & op_s2_i; // like above
227-
VMORNOT : simd_result = ~op_s1_i | op_s2_i; // like above
228-
VMNAND : simd_result = ~(op_s1_i & op_s2_i); // like above
229-
VMNOR : simd_result = ~(op_s1_i | op_s2_i); // like above
230-
VMXNOR : simd_result = ~(op_s1_i ^ op_s2_i); // like above
223+
VAND, VMAND : simd_result = op_s1_i & op_s2_i;
224+
VOR , VMOR : simd_result = op_s1_i | op_s2_i;
225+
VXOR, VMXOR : simd_result = op_s1_i ^ op_s2_i;
226+
VMANDNOT : simd_result = ~op_s1_i & op_s2_i;
227+
VMORNOT : simd_result = ~op_s1_i | op_s2_i;
228+
VMNAND : simd_result = ~(op_s1_i & op_s2_i);
229+
VMNOR : simd_result = ~(op_s1_i | op_s2_i);
230+
VMXNOR : simd_result = ~(op_s1_i ^ op_s2_i);
231231
VSLL : simd_result = shift_operand << shift_amount;
232232
VSRL : simd_result = shift_operand >> shift_amount;
233233
VSRA : simd_result = $signed(shift_operand) >>> shift_amount;

‎hw/ip/spatz/src/spatz_vfu.sv‎

Lines changed: 33 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -433,7 +433,7 @@ module spatz_vfu
433433
vrf_data_t [$clog2(N_FU)-1:0] reduction_q, reduction_d;
434434
vrf_data_t reduction_vector_data, reduction_scalar_data;
435435
`FF(reduction_q, reduction_d, '0)
436-
elen_t reduction_useless_value;
436+
elen_t reduction_neutral_value;
437437

438438
// IPU results
439439
logic [N_FU*ELEN-1:0] ipu_result;
@@ -616,62 +616,62 @@ module spatz_vfu
616616
logic [N_FU*ELEN-1:0] v0_mask; // bit mask to select the valid elements in v0.t for reduction instructions
617617
logic [N_FU*ELEN-1:0] mask; // bit mask
618618

619-
always_comb begin: reduction_useless_value_selection
620-
reduction_useless_value = '0;
619+
always_comb begin: reduction_neutral_value_selection
620+
reduction_neutral_value = '0;
621621
if(spatz_req.op_arith.is_reduction == 1'b1) begin
622622
case(spatz_req.op)
623623
VADD: // VREDSUM_VS, VFREDUSUM_VS, VFREDOSUM_VS
624-
reduction_useless_value = '0;
624+
reduction_neutral_value = '0;
625625
VAND: // VREDAND_VS:
626-
reduction_useless_value = '1;
626+
reduction_neutral_value = '1;
627627
VOR, // VREDOR_VS,
628628
VXOR: // VREDXOR_VS:
629-
reduction_useless_value = '0;
629+
reduction_neutral_value = '0;
630630
VMINU: // VREDMINU_VS:
631-
reduction_useless_value = '1;
631+
reduction_neutral_value = '1;
632632
VMIN: // VREDMIN_VS:
633633
unique case(spatz_req.vtype.vsew)
634-
EW_8:reduction_useless_value = {1'b0,7'h7f};
635-
EW_16:reduction_useless_value = {1'b0,15'h7fff};
636-
EW_32:reduction_useless_value = {1'b0,31'h7fffffff};
634+
EW_8:reduction_neutral_value = {1'b0,7'h7f};
635+
EW_16:reduction_neutral_value = {1'b0,15'h7fff};
636+
EW_32:reduction_neutral_value = {1'b0,31'h7fffffff};
637637
default:
638-
if(MAXEW == EW_64) reduction_useless_value = {1'b0,63'h7fffffffffffffff};
638+
if(MAXEW == EW_64) reduction_neutral_value = {1'b0,63'h7fffffffffffffff};
639639
endcase
640640
VMAXU: // VREDMAXU_VS
641-
reduction_useless_value = '0;
641+
reduction_neutral_value = '0;
642642
VMAX: // VREDMAX_VS
643643
unique case(spatz_req.vtype.vsew)
644-
EW_8:reduction_useless_value = {1'b1,7'h0};
645-
EW_16:reduction_useless_value = {1'b1,15'h0};
646-
EW_32:reduction_useless_value = {1'b1,31'h0};
644+
EW_8:reduction_neutral_value = {1'b1,7'h0};
645+
EW_16:reduction_neutral_value = {1'b1,15'h0};
646+
EW_32:reduction_neutral_value = {1'b1,31'h0};
647647
default:
648-
if(MAXEW == EW_64) reduction_useless_value = {1'b1,63'h0};
648+
if(MAXEW == EW_64) reduction_neutral_value = {1'b1,63'h0};
649649
endcase
650650
VFMINMAX: begin
651651
if(spatz_req.rm == fpnew_pkg::RNE) begin // VFREDMIN_VS
652652
unique case(fpu_src_fmt)
653653
// + infinity
654-
fpnew_pkg::FP64:reduction_useless_value = {1'b0,11'h7ff,52'h0};
655-
fpnew_pkg::FP32:reduction_useless_value = {1'b0,8'hff,23'h0};
656-
fpnew_pkg::FP16:reduction_useless_value = {1'b0,5'h1f,10'h0};
657-
fpnew_pkg::FP16ALT:reduction_useless_value = {1'b0,8'hff,7'h0};
658-
fpnew_pkg::FP8:reduction_useless_value = {1'b0,5'h1f,2'h0};
659-
fpnew_pkg::FP8ALT:reduction_useless_value = {1'b0,4'hf,3'h0};
654+
fpnew_pkg::FP64:reduction_neutral_value = {1'b0,11'h7ff,52'h0};
655+
fpnew_pkg::FP32:reduction_neutral_value = {1'b0,8'hff,23'h0};
656+
fpnew_pkg::FP16:reduction_neutral_value = {1'b0,5'h1f,10'h0};
657+
fpnew_pkg::FP16ALT:reduction_neutral_value = {1'b0,8'hff,7'h0};
658+
fpnew_pkg::FP8:reduction_neutral_value = {1'b0,5'h1f,2'h0};
659+
fpnew_pkg::FP8ALT:reduction_neutral_value = {1'b0,4'hf,3'h0};
660660
endcase
661661
end
662662
if (spatz_req.rm == fpnew_pkg::RTZ) begin // VFREDMAX_VS
663663
unique case(fpu_src_fmt)
664664
// - infinity
665-
fpnew_pkg::FP64:reduction_useless_value = {1'b1,11'h7ff,52'h0};
666-
fpnew_pkg::FP32:reduction_useless_value = {1'b1,8'hff,23'h0};
667-
fpnew_pkg::FP16:reduction_useless_value = {1'b1,5'h1f,10'h0};
668-
fpnew_pkg::FP16ALT:reduction_useless_value = {1'b1,8'hff,7'h0};
669-
fpnew_pkg::FP8:reduction_useless_value = {1'b1,5'h1f,2'h0};
670-
fpnew_pkg::FP8ALT:reduction_useless_value = {1'b1,4'hf,3'h0};
665+
fpnew_pkg::FP64:reduction_neutral_value = {1'b1,11'h7ff,52'h0};
666+
fpnew_pkg::FP32:reduction_neutral_value = {1'b1,8'hff,23'h0};
667+
fpnew_pkg::FP16:reduction_neutral_value = {1'b1,5'h1f,10'h0};
668+
fpnew_pkg::FP16ALT:reduction_neutral_value = {1'b1,8'hff,7'h0};
669+
fpnew_pkg::FP8:reduction_neutral_value = {1'b1,5'h1f,2'h0};
670+
fpnew_pkg::FP8ALT:reduction_neutral_value = {1'b1,4'hf,3'h0};
671671
endcase
672672
end
673673
end
674-
default: reduction_useless_value='0;
674+
default: reduction_neutral_value='0;
675675
endcase
676676
end
677677
end
@@ -757,14 +757,14 @@ module spatz_vfu
757757
// use of reduction useless value
758758
unique case (spatz_req.vtype.vsew)
759759
EW_8:
760-
reduction_vector_data = (vrf_rdata_i[1] & mask & v0_mask) | ({N_FU*(ELEN/8){reduction_useless_value[7:0]}} & ~(mask & v0_mask));
760+
reduction_vector_data = (vrf_rdata_i[1] & mask & v0_mask) | ({N_FU*(ELEN/8){reduction_neutral_value[7:0]}} & ~(mask & v0_mask));
761761
EW_16:
762-
reduction_vector_data = (vrf_rdata_i[1] & mask & v0_mask) | ({N_FU*(ELEN/16){reduction_useless_value[15:0]}} & ~(mask & v0_mask));
762+
reduction_vector_data = (vrf_rdata_i[1] & mask & v0_mask) | ({N_FU*(ELEN/16){reduction_neutral_value[15:0]}} & ~(mask & v0_mask));
763763
EW_32:
764-
reduction_vector_data = (vrf_rdata_i[1] & mask & v0_mask) | ({N_FU*(ELEN/32){reduction_useless_value[31:0]}} & ~(mask & v0_mask));
764+
reduction_vector_data = (vrf_rdata_i[1] & mask & v0_mask) | ({N_FU*(ELEN/32){reduction_neutral_value[31:0]}} & ~(mask & v0_mask));
765765
default:
766766
if (MAXEW == EW_64)
767-
reduction_vector_data = (vrf_rdata_i[1] & mask & v0_mask) | ({N_FU{reduction_useless_value[63:0]}} & ~(mask & v0_mask));
767+
reduction_vector_data = (vrf_rdata_i[1] & mask & v0_mask) | ({N_FU{reduction_neutral_value[63:0]}} & ~(mask & v0_mask));
768768
endcase
769769

770770
unique case (reduction_state_q)

‎hw/ip/spatz/src/spatz_vrf.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ module spatz_vrf
2020
input vrf_addr_t [NrWritePorts-1:0] waddr_i,
2121
input vrf_data_t [NrWritePorts-1:0] wdata_i,
2222
input logic [NrWritePorts-1:0] we_i,
23-
input vrf_be_t [NrWritePorts-1:0] wbe_i, // 32 bits* 3 WritePorts
23+
input vrf_be_t [NrWritePorts-1:0] wbe_i,
2424
output logic [NrWritePorts-1:0] wvalid_o,
2525
`ifdef BUF_FPU
2626
// Signal to track if result can be buffered or not
@@ -45,7 +45,7 @@ module spatz_vrf
4545
// Typedefs //
4646
//////////////
4747

48-
typedef logic [$bits(vrf_addr_t)-$clog2(NrVRFBanks)-1:0] vregfile_addr_t; // divide the addresses into banks.
48+
typedef logic [$bits(vrf_addr_t)-$clog2(NrVRFBanks)-1:0] vregfile_addr_t;
4949

5050
function automatic logic [$clog2(NrWordsPerBank)-1:0] f_vreg(vrf_addr_t addr);
5151
f_vreg = addr[$clog2(NrVRFWords)-1:$clog2(NrVRFBanks)];

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