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rgiuntirgiunti
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[SW/FIX] VSET for masking in load/store tests
1 parent 06522fa commit b92c84d

13 files changed

Lines changed: 250 additions & 122 deletions

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‎sw/riscvTests/CMakeLists.txt‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,6 @@ add_snitch_test(vadd isa/rv64uv/vadd.c)
3333
add_snitch_test(vsub isa/rv64uv/vsub.c)
3434
add_snitch_test(vrsub isa/rv64uv/vrsub.c)
3535

36-
add_snitch_test(vls isa/rv64uv/vls.c)
3736
add_snitch_test(vloxei isa/rv64uv/vloxei.c)
3837
add_snitch_test(vsuxei isa/rv64uv/vsuxei.c)
3938

‎sw/riscvTests/isa/rv64uv/vle16.c‎

Lines changed: 22 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -17,55 +17,69 @@ void TEST_CASE1(void) {
1717

1818
//*******Checking functionality of vle16 with different values of masking register******//
1919
void TEST_CASE2(void) {
20+
VSET(2, e8, m1);
21+
VCLEAR(v0);
22+
VLOAD_8(v0, 0xFF, 0xFF);
23+
2024
VSET(16, e16, m1);
2125
volatile uint16_t INP1[] = {0xFFe0, 0xFFd3, 0xFF40, 0xFFd1, 0xFF84, 0xFF48, 0xFF89, 0xFF88,
2226
0xFF88, 0xFFae, 0xFF08, 0xFF91, 0xFF02, 0xFF59, 0xFF11, 0xFF89};
2327
VCLEAR(v1);
24-
VLOAD_8(v0, 0xFF, 0xFF);
25-
VSET(16, e16, m1);
2628
asm volatile("vle16.v v1, (%0), v0.t" ::"r"(INP1));
2729
VCMP_U16(2, v1, 0xFFe0, 0xFFd3, 0xFF40, 0xFFd1, 0xFF84, 0xFF48, 0xFF89, 0xFF88,
2830
0xFF88, 0xFFae, 0xFF08, 0xFF91, 0xFF02, 0xFF59, 0xFF11, 0xFF89);
2931
}
3032

3133
void TEST_CASE3(void) {
34+
VSET(2, e8, m1);
35+
VCLEAR(v0);
36+
VLOAD_8(v0, 0x00, 0x00);
37+
3238
VSET(16, e16, m1);
3339
volatile uint16_t INP1[] = {0xFFe0, 0xFFd3, 0xFF40, 0xFFd1, 0xFF84, 0xFF48, 0xFF89, 0xFF88,
3440
0xFF88, 0xFFae, 0xFF08, 0xFF91, 0xFF02, 0xFF59, 0xFF11, 0xFF89};
3541
VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
36-
VLOAD_8(v0, 0x00, 0x00);
37-
VSET(16, e16, m1);
3842
asm volatile("vle16.v v1, (%0), v0.t" ::"r"(INP1));
3943
VCMP_U16(3, v1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
4044
}
4145

4246
void TEST_CASE4(void) {
47+
VSET(2, e8, m1);
48+
VCLEAR(v0);
49+
VLOAD_8(v0, 0xAA, 0xAA);
50+
4351
VSET(16, e16, m1);
4452
volatile uint16_t INP1[] = {0xFFe0, 0xFFd3, 0xFF40, 0xFFd1, 0xFF84, 0xFF48, 0xFF89, 0xFF88,
4553
0xFF88, 0xFFae, 0xFF08, 0xFF91, 0xFF02, 0xFF59, 0xFF11, 0xFF89};
4654
VCLEAR(v1);
4755
VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
48-
VLOAD_8(v0, 0xAA, 0xAA);
49-
VSET(16, e16, m1);
56+
5057
asm volatile("vle16.v v1, (%0), v0.t" ::"r"(INP1));
5158
VCMP_U16(4, v1, 1, 0xFFd3, 3, 0xFFd1, 5, 0xFF48, 7, 0xFF88,
5259
9, 0xFFae, 11, 0xFF91, 13, 0xFF59, 15, 0xFF89);
5360
}
5461

5562
void TEST_CASE5(void) {
63+
VSET(2, e8, m1);
64+
VCLEAR(v0);
65+
VLOAD_8(v0, 0xAA, 0xAA);
66+
5667
VSET(16, e16, m8);
5768
volatile uint16_t INP1[] = {0xFFe0, 0xFFd3, 0xFF40, 0xFFd1, 0xFF84, 0xFF48, 0xFF89, 0xFF88,
5869
0xFF88, 0xFFae, 0xFF08, 0xFF91, 0xFF02, 0xFF59, 0xFF11, 0xFF89};
5970
VCLEAR(v8);
6071
VLOAD_16(v8, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
61-
VLOAD_8(v0, 0xAA, 0xAA);
62-
VSET(16, e16, m8);
72+
6373
asm volatile("vle16.v v8, (%0), v0.t" ::"r"(INP1));
6474
VCMP_U16(5, v8, 1, 0xFFd3, 3, 0xFFd1, 5, 0xFF48, 7, 0xFF88,
6575
9, 0xFFae, 11, 0xFF91, 13, 0xFF59, 15, 0xFF89);
6676
}
6777

6878
void TEST_CASE6(void) {
79+
VSET(8, e8, m1);
80+
VCLEAR(v0);
81+
VLOAD_8(v0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA);
82+
6983
VSET(64, e16, m8);
7084
volatile uint16_t INP1[] = {
7185
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
@@ -83,9 +97,6 @@ void TEST_CASE6(void) {
8397
33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
8498
49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
8599

86-
87-
VLOAD_8(v0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA);
88-
VSET(64, e16, m8);
89100
asm volatile("vle16.v v8, (%0), v0.t" ::"r"(INP1));
90101
VCMP_U16(6, v8, 1, 0x0001, 3, 0x0003, 5, 0x0005, 7, 0x0007, 9, 0x0009, 11, 0x000B, 13, 0x000D, 15, 0x000F,
91102
17, 0x0011, 19, 0x0013, 21, 0x0015, 23, 0x0017, 25, 0x0019,27, 0x001B, 29, 0x001D, 31, 0x001F,

‎sw/riscvTests/isa/rv64uv/vle32.c‎

Lines changed: 31 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -17,48 +17,57 @@ void TEST_CASE1(void) {
1717

1818
//*******Checking functionality of vle32 with different values of masking register******//
1919
void TEST_CASE2(void) {
20-
VSET(8, e32, m1);
21-
volatile uint32_t INP1[] = {0xDEADBEe0, 0xDEADBEd3, 0xDEADBE40, 0xDEADBEd1,
22-
0xDEADBE84, 0xDEADBE48, 0xDEADBE89, 0xDEADBE88};
23-
VCLEAR(v1);
20+
volatile uint32_t INP1[] = {0xDEADBE00, 0xDEADBE9f, 0xDEADBEe4, 0xDEADBE19,
21+
0xDEADBE20, 0xDEADBE8f, 0xDEADBE2e, 0xDEADBE05};
22+
VSET(1, e8, m1);
23+
VCLEAR(v0);
2424
VLOAD_8(v0, 0xFF);
25+
2526
VSET(8, e32, m1);
27+
VCLEAR(v1);
2628
asm volatile("vle32.v v1, (%0), v0.t" ::"r"(INP1));
27-
VCMP_U32(2, v1, 0xDEADBEe0, 0xDEADBEd3, 0xDEADBE40, 0xDEADBEd1,
28-
0xDEADBE84, 0xDEADBE48, 0xDEADBE89, 0xDEADBE88);
29+
VCMP_U32(2, v1, 0xDEADBE00, 0xDEADBE9f, 0xDEADBEe4, 0xDEADBE19,
30+
0xDEADBE20, 0xDEADBE8f, 0xDEADBE2e, 0xDEADBE05);
2931
}
3032

3133
void TEST_CASE3(void) {
32-
VSET(8, e32, m1);
3334
volatile uint32_t INP1[] = {0xDEADBEe0, 0xDEADBEd3, 0xDEADBE40, 0xDEADBEd1,
3435
0xDEADBE84, 0xDEADBE48, 0xDEADBE89, 0xDEADBE88};
35-
VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8);
36+
VSET(1, e8, m1);
37+
VCLEAR(v0);
3638
VLOAD_8(v0, 0x00);
39+
3740
VSET(8, e32, m1);
41+
VCLEAR(v1);
42+
VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8);
3843
asm volatile("vle32.v v1, (%0), v0.t" ::"r"(INP1));
3944
VCMP_U32(3, v1, 1, 2, 3, 4, 5, 6, 7, 8);
4045
}
4146

4247
void TEST_CASE4(void) {
43-
VSET(8, e32, m1);
4448
volatile uint32_t INP1[] = {0xDEADBEe0, 0xDEADBEd3, 0xDEADBE40, 0xDEADBEd1,
4549
0xDEADBE84, 0xDEADBE48, 0xDEADBE89, 0xDEADBE88};
46-
VCLEAR(v1);
47-
VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8);
50+
VSET(1, e8, m1);
51+
VCLEAR(v0);
4852
VLOAD_8(v0, 0xAA);
53+
4954
VSET(8, e32, m1);
55+
VCLEAR(v1);
56+
VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8);
5057
asm volatile("vle32.v v1, (%0), v0.t" ::"r"(INP1));
5158
VCMP_U32(4, v1, 1, 0xDEADBEd3, 3, 0xDEADBEd1, 5, 0xDEADBE48, 7, 0xDEADBE88);
5259
}
5360

5461
void TEST_CASE5(void) {
55-
VSET(8, e32, m8);
5662
volatile uint32_t INP1[] = {0xDEADBEe0, 0xDEADBEd3, 0xDEADBE40, 0xDEADBEd1,
5763
0xDEADBE84, 0xDEADBE48, 0xDEADBE89, 0xDEADBE88};
58-
VCLEAR(v8);
59-
VLOAD_32(v8, 1, 2, 3, 4, 5, 6, 7, 8);
64+
VSET(1, e8, m1);
65+
VCLEAR(v0);
6066
VLOAD_8(v0, 0xAA);
67+
6168
VSET(8, e32, m8);
69+
VCLEAR(v8);
70+
VLOAD_32(v8, 1, 2, 3, 4, 5, 6, 7, 8);
6271
asm volatile("vle32.v v8, (%0), v0.t" ::"r"(INP1));
6372
VCMP_U32(5, v8, 1, 0xDEADBEd3, 3, 0xDEADBEd1, 5, 0xDEADBE48, 7, 0xDEADBE88);
6473
}
@@ -92,10 +101,9 @@ void TEST_CASE6(void) {
92101
0x0000001C, 0x0000001D, 0x0000001E, 0x0000001F);
93102
}
94103

95-
//NB: alignment is a workarounfd for a bug in the implementation of doublebw_vlsu, and should be removed once the bug is fixed
96104
void TEST_CASE7(void) {
97105
VSET(64, e32, m8);
98-
volatile uint32_t __attribute__((aligned(8))) INP1[] = {
106+
volatile uint32_t INP1[] = {
99107
0x00000000, 0x00000001, 0x00000002, 0x00000003,
100108
0x00000004, 0x00000005, 0x00000006, 0x00000007,
101109
0x00000008, 0x00000009, 0x0000000A, 0x0000000B,
@@ -141,9 +149,9 @@ void TEST_CASE7(void) {
141149
0x0000003C, 0x0000003D, 0x0000003E, 0x0000003F);
142150
}
143151

152+
// TODO
144153
void TEST_CASE8(void) {
145-
VSET(64, e32, m8);
146-
volatile uint32_t __attribute__((aligned(8))) INP1[] = {
154+
volatile uint32_t INP1[] = {
147155
0x00000000, 0x00000001, 0x00000002, 0x00000003,
148156
0x00000004, 0x00000005, 0x00000006, 0x00000007,
149157
0x00000008, 0x00000009, 0x0000000A, 0x0000000B,
@@ -165,8 +173,12 @@ void TEST_CASE8(void) {
165173
0x0000003C, 0x0000003D, 0x0000003E, 0x0000003F
166174
};
167175

168-
VCLEAR(v8);
176+
VSET(8, e8, m1);
177+
VCLEAR(v0);
178+
VLOAD_8(v0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAB, 0xAB, 0xAB, 0xAB);
169179

180+
VSET(64, e32, m8);
181+
VCLEAR(v8);
170182
VLOAD_32(v8,
171183
99, 99, 99, 99, 99, 99, 99, 99,
172184
99, 99, 99, 99, 99, 99, 99, 99,
@@ -177,11 +189,6 @@ void TEST_CASE8(void) {
177189
99, 99, 99, 99, 99, 99, 99, 99,
178190
99, 99, 99, 99, 99, 99, 99, 99);
179191

180-
VLOAD_8(v0, 0xAA, 0xAA, 0xAA, 0xAA,
181-
0xAB, 0xAB, 0xAB, 0xAB);
182-
183-
VSET(64, e32, m8);
184-
185192
asm volatile("vle32.v v8, (%0), v0.t" ::"r"(INP1));
186193

187194
VCMP_U32(8, v8,

‎sw/riscvTests/isa/rv64uv/vle64.c‎

Lines changed: 24 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -17,47 +17,59 @@ void TEST_CASE1(void) {
1717

1818
//*******Checking functionality of vle64 with different values of masking register******//
1919
void TEST_CASE2(void) {
20+
VSET(1, e8, m1);
21+
VCLEAR(v0);
22+
VLOAD_8(v0, 0x0F);
23+
2024
VSET(4, e64, m1);
2125
volatile uint64_t INP1[] = {0xDEADBEEFCAFE00e0, 0xDEADBEEFCAFE00d3,
2226
0xDEADBEEFCAFE0040, 0xDEADBEEFCAFE00d1};
2327
VCLEAR(v1);
24-
VLOAD_8(v0, 0x0F);
25-
VSET(4, e64, m1);
28+
2629
asm volatile("vle64.v v1, (%0), v0.t" ::"r"(INP1));
2730
VCMP_U64(2, v1, 0xDEADBEEFCAFE00e0, 0xDEADBEEFCAFE00d3,
2831
0xDEADBEEFCAFE0040, 0xDEADBEEFCAFE00d1);
2932
}
3033

3134
void TEST_CASE3(void) {
35+
VSET(1, e8, m1);
36+
VCLEAR(v0);
37+
VLOAD_8(v0, 0x00);
38+
3239
VSET(4, e64, m1);
3340
volatile uint64_t INP1[] = {0xDEADBEEFCAFE00e0, 0xDEADBEEFCAFE00d3,
3441
0xDEADBEEFCAFE0040, 0xDEADBEEFCAFE00d1};
42+
VCLEAR(v1);
3543
VLOAD_64(v1, 1, 2, 3, 4);
36-
VLOAD_8(v0, 0x00);
37-
VSET(4, e64, m1);
3844
asm volatile("vle64.v v1, (%0), v0.t" ::"r"(INP1));
3945
VCMP_U64(3, v1, 1, 2, 3, 4);
4046
}
4147

4248
void TEST_CASE4(void) {
49+
VSET(1, e8, m1);
50+
VCLEAR(v0);
51+
VLOAD_8(v0, 0x0A);
52+
4353
VSET(4, e64, m1);
4454
volatile uint64_t INP1[] = {0xDEADBEEFCAFE00e0, 0xDEADBEEFCAFE00d3,
4555
0xDEADBEEFCAFE0040, 0xDEADBEEFCAFE00d1};
4656
VCLEAR(v1);
4757
VLOAD_64(v1, 1, 2, 3, 4);
48-
VLOAD_8(v0, 0x0A);
4958
VSET(4, e64, m1);
5059
asm volatile("vle64.v v1, (%0), v0.t" ::"r"(INP1));
5160
VCMP_U64(4, v1, 1, 0xDEADBEEFCAFE00d3, 3, 0xDEADBEEFCAFE00d1);
5261
}
5362

5463
void TEST_CASE5(void) {
64+
VSET(1, e8, m1);
65+
VCLEAR(v0);
66+
VLOAD_8(v0, 0x0A);
67+
5568
VSET(4, e64, m8);
5669
volatile uint64_t INP1[] = {0xDEADBEEFCAFE00e0, 0xDEADBEEFCAFE00d3,
5770
0xDEADBEEFCAFE0040, 0xDEADBEEFCAFE00d1};
5871
VCLEAR(v8);
5972
VLOAD_64(v8, 1, 2, 3, 4);
60-
VLOAD_8(v0, 0x0A);
6173
VSET(4, e64, m8);
6274
asm volatile("vle64.v v8, (%0), v0.t" ::"r"(INP1));
6375
VCMP_U64(5, v8, 1, 0xDEADBEEFCAFE00d3, 3, 0xDEADBEEFCAFE00d1);
@@ -81,10 +93,9 @@ void TEST_CASE6(void) {
8193
0x000000000000000C, 0x000000000000000D, 0x000000000000000E, 0x000000000000000F);
8294
}
8395

84-
//NB: alignment is a workarounfd for a bug in the implementation of doublebw_vlsu, and should be removed once the bug is fixed
8596
void TEST_CASE7(void) {
8697
VSET(32, e64, m8);
87-
volatile uint64_t __attribute__((aligned(8))) INP1[] = {
98+
volatile uint64_t INP1[] = {
8899
0x0000000000000000, 0x0000000000000001, 0x0000000000000002, 0x0000000000000003,
89100
0x0000000000000004, 0x0000000000000005, 0x0000000000000006, 0x0000000000000007,
90101
0x0000000000000008, 0x0000000000000009, 0x000000000000000A, 0x000000000000000B,
@@ -110,9 +121,12 @@ void TEST_CASE7(void) {
110121
}
111122

112123
void TEST_CASE8(void) {
113-
VSET(32, e64, m8);
124+
VSET(4, e8, m1);
125+
VCLEAR(v0);
126+
VLOAD_8(v0, 0xAB, 0xAB, 0xAA, 0xAA);
114127

115-
volatile uint64_t __attribute__((aligned(8))) INP1[] = {
128+
VSET(32, e64, m8);
129+
volatile uint64_t INP1[] = {
116130
0x0000000000000000, 0x0000000000000001, 0x0000000000000002, 0x0000000000000003,
117131
0x0000000000000004, 0x0000000000000005, 0x0000000000000006, 0x0000000000000007,
118132
0x0000000000000008, 0x0000000000000009, 0x000000000000000A, 0x000000000000000B,
@@ -133,8 +147,6 @@ void TEST_CASE8(void) {
133147

134148
VLOAD_8(v0, 0xAB, 0xAB, 0xAA, 0xAA);
135149

136-
VSET(32, e64, m8);
137-
138150
asm volatile("vle64.v v8, (%0), v0.t" ::"r"(INP1));
139151

140152
VCMP_U64(8, v8,

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