@@ -220,14 +220,14 @@ module spatz_simd_lane import spatz_pkg::*; import rvv_pkg::vew_e; #(
220220 VSUB , VRSUB , VNMSAC , VNMSUB , VSBC : simd_result = subtractor_result[Width- 1 : 0 ];
221221 VMIN , VMINU : simd_result = $signed ({ op_s1_i[Width- 1 ] & is_signed_i, op_s1_i} ) <= $signed ({ op_s2_i[Width- 1 ] & is_signed_i, op_s2_i} ) ? op_s1_i : op_s2_i;
222222 VMAX , VMAXU : simd_result = $signed ({ op_s1_i[Width- 1 ] & is_signed_i, op_s1_i} ) > $signed ({ op_s2_i[Width- 1 ] & is_signed_i, op_s2_i} ) ? op_s1_i : op_s2_i;
223- VAND , VMAND : simd_result = op_s1_i & op_s2_i; // CMY: add masking support
224- VOR , VMOR : simd_result = op_s1_i | op_s2_i; // like above
225- VXOR , VMXOR : simd_result = op_s1_i ^ op_s2_i; // like above
226- VMANDNOT : simd_result = ~ op_s1_i & op_s2_i; // like above
227- VMORNOT : simd_result = ~ op_s1_i | op_s2_i; // like above
228- VMNAND : simd_result = ~ (op_s1_i & op_s2_i); // like above
229- VMNOR : simd_result = ~ (op_s1_i | op_s2_i); // like above
230- VMXNOR : simd_result = ~ (op_s1_i ^ op_s2_i); // like above
223+ VAND , VMAND : simd_result = op_s1_i & op_s2_i;
224+ VOR , VMOR : simd_result = op_s1_i | op_s2_i;
225+ VXOR , VMXOR : simd_result = op_s1_i ^ op_s2_i;
226+ VMANDNOT : simd_result = ~ op_s1_i & op_s2_i;
227+ VMORNOT : simd_result = ~ op_s1_i | op_s2_i;
228+ VMNAND : simd_result = ~ (op_s1_i & op_s2_i);
229+ VMNOR : simd_result = ~ (op_s1_i | op_s2_i);
230+ VMXNOR : simd_result = ~ (op_s1_i ^ op_s2_i);
231231 VSLL : simd_result = shift_operand << shift_amount;
232232 VSRL : simd_result = shift_operand >> shift_amount;
233233 VSRA : simd_result = $signed (shift_operand) >>> shift_amount;
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