VLSU Fix#105
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Jun 12, 2026
Navaneeth-KunhiPurayil
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Thanks for the fixes. Looks good to me. The test cases are also good.
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Problem: indexed/strided/misaligned loads with small vsew write only a few bytes per cycle to a full VRFWordWidth-wide word (wbe is sparse). Each partial write still generates vrf_wvalid, which the controller treats as a full write-credit and enables chaining too early, producing wrong results.
Fix: accumulate partial writes into a single coalescing buffer. Only present the write to the VRF (assert vrf_we_o) when the accumulated wbe covers the full word (&wbe == 1) OR when rsp_valid marks the last write of the instruction (handles a non-full tail word). The response to the controller is also gated on the coalesced commit so that chaining is only enabled after the entire VRF word is coherent.
TODO: same fix needed also for VFU and VSLDU