Fix NaN-boxing and sign extension of narrow scalar FP moves

[Smephite]

Summary

The FPU sequencer mishandles both directions of narrow scalar moves between the GPR and FP register files:

• GPR→FPR (fmv.s.x, fmv.h.x, fmv.b.x): the value written to the FPR was the raw sign-extended operand from Snitch instead of a NaN-boxed one. Narrow values are required to be extended with '1.
• FPR→GPR (fmv.x.h, fmv.x.b): the move result forwarded the raw FPR word, so the upper GPR bits came from the NaN-box (all 1s) instead of sign-extending the narrow value. Positive half/byte float read back as 0xFFFFxxxx / 0xFFFFFFxx.

This PR fixes this issue by handling the different widths and extending / truncating accordingly.

Testing

New regression test riscvTests/fmv_narrow covers both directions:

• TC1–TC4: FPR→GPR sign extension via round-trips (positive + negative half/byte, fmv.x.s control)
• TC5–TC7: GPR→FPR NaN-boxing, observed by reading the FPR back wider than the move wrote it (fmv.x.s for the 16/8-bit boxes, fsd for the upper 32 box bits on FLEN=64)