Merge pull request #113 from pulseengine/chore/v0.5.0-release-prep

chore: bump to v0.5.0

Author: avrabe

AGENTS.md

@@ -8,8 +8,8 @@
 
 This project uses **Rivet** for SDLC artifact traceability.
 - Config: `rivet.yaml`
-- Schemas: common, dev, aspice, stpa, aadl
-- Artifacts: 342 across 3 types
+- Schemas: common, dev, aspice, stpa, aadl, sysml2
+- Artifacts: 359 across 3 types
 - Validation: `rivet validate` (current status: pass)
 
 ## Available Commands
@@ -31,8 +31,8 @@ This project uses **Rivet** for SDLC artifact traceability.
 
 | Type | Count | Description |
 |------|------:|-------------|
-| `design-decision` | 65 | An architectural or design decision with rationale |
-| `feature` | 103 | A user-visible capability or feature |
+| `design-decision` | 72 | An architectural or design decision with rationale |
+| `feature` | 113 | A user-visible capability or feature |
 | `requirement` | 174 | A functional or non-functional requirement |
 | `aadl-analysis-result` | 0 | Output of a spar analysis pass |
 | `aadl-component` | 0 | AADL component type or implementation imported from spar |
@@ -54,6 +54,10 @@ This project uses **Rivet** for SDLC artifact traceability.
 | `sw-verification` | 0 | Software verification measure against SW requirements (SWE.6 — Software Verification) |
 | `sys-integration-verification` | 0 | System integration and integration verification measure (SYS.4 — System Integration and Integration Verification) |
 | `sys-verification` | 0 | System verification measure against system requirements (SYS.5 — System Verification) |
+| `sysml-action` | 0 | SysML v2 action definition (behavioral) |
+| `sysml-component` | 0 | SysML v2 part definition or usage |
+| `sysml-interface` | 0 | SysML v2 interface or port definition |
+| `sysml-requirement` | 0 | SysML v2 requirement (def or usage) |
 | `system-arch-component` | 0 | System architectural element (SYS.3) |
 | `system-constraint` | 0 | A condition or behavior that must be satisfied to prevent a hazard. Each constraint is the inversion of a hazard. |
 | `system-req` | 0 | System requirement derived from stakeholder needs (SYS.2) |

COMPLIANCE.md

@@ -1,24 +1,24 @@
 # AS5506 AADL v2.2 Compliance Gap Analysis
 
-**Updated**: 2026-03-08
+**Updated**: 2026-04-06 (v0.5.0)
 **Source**: 102 HTML files from OSATE2 (`org.osate.help/html/std/`)
-**Toolchain**: spar (581 tests passing across 10 crates)
+**Toolchain**: spar (1200+ tests passing across 16 crates)
 
 ---
 
 ## Executive Summary
 
 | Layer | Status | Score |
 |-------|--------|-------|
-| **Parser (syntax)** | Excellent | ~95% — all major constructs parsed |
-| **ItemTree (declaration capture)** | Good | ~85% — modes, prototypes, calls, flow impls, array dims, in_modes |
-| **Name Resolution** | Partial | ~50% — cross-file resolution + naming rule validation |
+| **Parser (syntax)** | Excellent | ~95% — all major constructs parsed, doubled-quote strings |
+| **ItemTree (declaration capture)** | Good | ~85% — modes, prototypes, calls, flow impls, array dims, in_modes, requires_modes |
+| **Name Resolution** | Partial | ~55% — cross-file resolution + naming rules + duplicate package detection |
 | **Legality Rules (L-rules)** | Partial | ~15% — engine scaffold with ~20 rules from 6 categories |
 | **Naming Rules (N-rules)** | Partial | ~25% — duplicate detection, with-clause hygiene, scope uniqueness |
-| **Instance Model** | Good | ~65% — hierarchy + modes + semantic connections + features |
-| **Property System** | Partial | ~45% — typed PropertyExpr (13 variants), type checking, unit conversion |
-| **Modes** | Good | ~55% — in ItemTree + instance model, mode check analysis |
-| **Predeclared Property Sets** | Good | ~90% — 8/8 sets, 104 properties |
+| **Instance Model** | Good | ~80% — hierarchy + modes + semantic connections + features + **extends inheritance** |
+| **Property System** | Good | ~65% — typed PropertyExpr (14 variants), text fallback parser, unit conversion |
+| **Modes** | Good | ~65% — in ItemTree + instance model + requires_modes + modal filtering |
+| **Predeclared Property Sets** | Good | ~90% — 8/8 sets, 102 properties (corrected classifications) |
 
 ---
 

Cargo.toml

@@ -19,7 +19,7 @@ members = [
 ]
 
 [workspace.package]
-version = "0.4.0"
+version = "0.5.0"
 edition = "2024"
 license = "MIT"
 repository = "https://github.com/pulseengine/spar"

artifacts/architecture.yaml

@@ -155,9 +155,10 @@ artifacts:
     type: design-decision
     title: spar-analysis
     description: >
-      27 analysis passes implementing connectivity, scheduling, latency,
+      33+ analysis passes implementing connectivity, scheduling, latency,
       resource budget, EMV2, ARINC 653, legality rules, mode reachability,
-      and more. Trait-based Analysis framework with AnalysisRunner.
+      AI/ML safety (ISO/PAS 8800), and more. Trait-based Analysis framework
+      with AnalysisRunner.
     fields:
       rationale: >
         Trait-based Analysis framework allows modular registration of
@@ -823,3 +824,136 @@ artifacts:
   # ── SysML v2 Integration (v0.5.0) ───────────────────────────────────
 
   # ARCH-SYSML2-001 merged into ARCH-SYSML2-002 and ARCH-SYSML2-003 (v0.4.0)
+
+  # ── v0.5.0 Architecture Decisions ──────────────────────────────────
+
+  - id: ARCH-EXTENDS
+    type: design-decision
+    title: Type inheritance via extends chain walking
+    description: >
+      collect_type_chain_features and collect_impl_chain walk the extends
+      chain recursively with cycle detection. Features deduplicated by name.
+    status: implemented
+    fields:
+      rationale: >
+        Recursive chain walking mirrors the AADL spec semantics for extends.
+        Cycle detection prevents infinite loops. Name-based deduplication
+        ensures refined features override parent features correctly.
+    tags: [v0.5.0]
+    links:
+      - type: satisfies
+        target: REQ-MODEL-005
+
+  - id: ARCH-SYSML2-SCHEMA
+    type: design-decision
+    title: SysML v2 Rivet schema
+    description: >
+      schemas/sysml2.yaml defines sysml-requirement, sysml-component,
+      sysml-interface, sysml-action artifact types for rivet integration.
+    status: implemented
+    fields:
+      rationale: >
+        Custom rivet artifact types enable SysML v2 elements to participate
+        natively in traceability graphs. Schema-level typing ensures
+        validation and consistent extraction output.
+    tags: [v0.5.0, sysml2]
+    links:
+      - type: satisfies
+        target: REQ-SYSML2-EXTRACT
+
+  - id: ARCH-AIML
+    type: design-decision
+    title: AI/ML analysis passes following ISO/PAS 8800
+    description: >
+      Six analysis modules for AI/ML component safety: inference deadline
+      checking, fallback coverage, fallback timing, OOD coverage,
+      model deployment validation, and redundancy verification. Each
+      implements the Analysis trait and integrates with AnalysisRunner.
+    status: implemented
+    fields:
+      rationale: >
+        ISO/PAS 8800 mandates safety analysis for AI/ML components in
+        automotive systems. Implementing as standard Analysis trait modules
+        ensures they integrate with existing AnalysisRunner and benefit
+        from the same reporting infrastructure.
+    tags: [v0.5.0, analysis, ai-ml]
+    links:
+      - type: satisfies
+        target: REQ-ANALYSIS-001
+
+  - id: ARCH-EMV2-STPA
+    type: design-decision
+    title: EMV2 fault tree to STPA hazard mapping
+    description: >
+      Bridge module mapping EMV2 composite error states to STPA hazards
+      and propagation paths to loss scenarios. Enables safety analysis
+      workflows spanning both EMV2 and STPA methodologies.
+    status: implemented
+    fields:
+      rationale: >
+        STPA and EMV2 address overlapping safety concerns from different
+        perspectives. Bridging them avoids duplicate modeling effort and
+        enables cross-methodology traceability in safety cases.
+    tags: [v0.5.0, safety]
+    links:
+      - type: satisfies
+        target: REQ-ANALYSIS-005
+
+  - id: ARCH-MODAL-FILTER
+    type: design-decision
+    title: Modal filtering with requires_modes flag
+    description: >
+      requires_modes flag stored in ItemTree during lowering.
+      is_active_in_mode utility enables modal-aware connectivity
+      and scheduling analysis without re-instantiation.
+    status: implemented
+    fields:
+      rationale: >
+        Storing requires_modes in ItemTree at lowering time avoids
+        re-parsing CST during analysis. The is_active_in_mode utility
+        provides a single filtering point for all modal-aware passes.
+    tags: [v0.5.0, modes]
+    links:
+      - type: satisfies
+        target: REQ-ANALYSIS-009
+
+  - id: ARCH-PROP-LOWERING
+    type: design-decision
+    title: Property CST lowering with text fallback parser
+    description: >
+      When CST lowering cannot determine property value type, a text-based
+      fallback parser handles booleans, references, classifiers, ranges,
+      lists, numerics with units, and enums. Covers legacy and mixed-version
+      AADL property syntax gracefully.
+    status: implemented
+    fields:
+      rationale: >
+        CST lowering sometimes lacks enough context to determine property
+        value types (especially for user-defined property sets). A text
+        fallback parser provides graceful degradation while maintaining
+        typed values for downstream analysis.
+    tags: [v0.5.0, properties]
+    links:
+      - type: satisfies
+        target: REQ-PROP-002
+
+  - id: ARCH-SECURITY-HARDEN
+    type: design-decision
+    title: Security hardening across rendering and CLI
+    description: >
+      22 correctness and security fixes from adversarial scanning: XSS
+      prevention via HTML entity escaping in SVG output, YAML/TOML
+      injection prevention via safe serialization, path traversal guards
+      on file operations, UTF-8 safe percent decoding, arena index
+      bounds checks preventing panics on invalid input.
+    status: implemented
+    fields:
+      rationale: >
+        Adversarial scanning revealed input-driven vulnerabilities in
+        rendering and CLI paths. Defense-in-depth approach hardens each
+        layer independently: output escaping, input validation, and
+        bounds checking.
+    tags: [v0.5.0, security]
+    links:
+      - type: satisfies
+        target: STPA-SEC-REQ-001

artifacts/requirements.yaml

@@ -72,7 +72,7 @@ artifacts:
     description: >
       Support component type extension, implementation extension,
       feature refinement, and subcomponent refinement.
-    status: partial
+    status: implemented
     tags: [model, as5506-ch4]
 
   # ── Name Resolution (AS5506 Ch.4) ──────────────────────────────────────
@@ -152,7 +152,7 @@ artifacts:
       Evaluate all property expression types: integer, real, string,
       boolean, enumeration, list, record, range, classifier, reference,
       computed values, unit literals.
-    status: partial
+    status: implemented
     tags: [properties, as5506-ch11]
 
   - id: REQ-PROP-003
@@ -498,10 +498,9 @@ artifacts:
     type: requirement
     title: Known analysis gaps
     description: >
-      Not yet covered: Ch.6 (type extensions — partial in extends_rules.rs),
-      Ch.7 (prototypes — parsed but not analyzed), property expression
-      evaluation (value(), arithmetic, record field access). See also
-      REQ-PROP-002 (partial).
+      Not yet covered: Ch.7 (prototypes — parsed but not analyzed).
+      Ch.6 type extensions now resolved via extends chain walking (v0.5.0).
+      Property expression evaluation now covered by text fallback parser (v0.5.0).
     status: partial
     links:
       - type: satisfies
@@ -864,7 +863,7 @@ artifacts:
       notation. Hand-written recursive descent, lossless CST, error recovery.
       Same architecture as spar-parser. Covers KerML kernel + SysML v2 profile
       (part, port, connection, requirement, constraint, action, state).
-    status: planned
+    status: implemented
     tags: [sysml2, parser, v040]
     links:
       - type: traces-to
@@ -878,7 +877,7 @@ artifacts:
       part def → system/process type, port def → data port, connection def →
       connection, constraint def → timing properties, allocate → bindings.
       Enables spar analysis on SysML v2-modeled systems.
-    status: planned
+    status: implemented
     tags: [sysml2, transform, v040]
     links:
       - type: traces-to
@@ -892,7 +891,7 @@ artifacts:
       requirement artifacts with satisfy/verify links preserved. Bridges
       SysML v2 requirement management with rivet traceability. Links map:
       SysML satisfy → rivet satisfies, SysML verify → rivet verifies.
-    status: planned
+    status: implemented
     tags: [sysml2, requirements, rivet, v040]
     links:
       - type: traces-to
@@ -967,7 +966,7 @@ artifacts:
       Result: SysML v2 (system-level) → AADL (deployment-level) →
       WIT/code (implementation-level), with rivet tracing through all
       three layers and spar analyzing architecture at every level.
-    status: planned
+    status: implemented
     tags: [transform, sysml, interop, v050]
     links:
       - type: traces-to