pbdrv: adc: ev3: Improve ADC settling time.

Using the max SPI SCLK speed of 20 MHz, the ADC is not able to read up
to the full 5V but rather reading somewhere around 50 mV less.

By slowing down the SCLK rate, we give the ADC more time to settle after
switching the mux and can get more accurate readings as a result.
Testing has shown that 1 MHz slow enough to achieve this.

Author: dlech

lib/pbio/drv/block_device/block_device_ev3.c

@@ -79,11 +79,11 @@ enum {
  */
 enum {
     // The maximum ADC clock speed according to the datasheet is 20 MHz.
-    // However, because the SPI peripheral does not have a fractional clock generator,
-    // the closest achievable in-spec speed is a division factor of 8.
-    //
-    // 150 MHz / 8 = 18.75 MHz actual
-    ADC_SPI_CLK_SPEED = 20000000,
+    // However, likely due to capacitance, it takes more time to settle even
+    // when maxing out other delays like C2T/T2C/WDELAY. Slowing down the
+    // SCLK adds even more settling time since each CS triggers a conversion
+    // and triggers the acquisition of the previous conversion.
+    ADC_SPI_CLK_SPEED = 1000000,
     // Time between the end of one SPI operation and start of the next.
     ADC_SAMPLE_PERIOD = 2,
 };