pbio/platform/ev3/platform.c: Initial MMU setup

This creates an identity mapping for only the valid bits of
the address space. It also adds logic to the exception handler
to print out fault addresses.

This currently marks the entire address space as uncacheable.
Drivers will need to be updated to take caches into account
before we can mark RAM as cacheable.

Author: ArcaneNibble

lib/pbio/platform/ev3/platform.c

@@ -41,6 +41,7 @@
 #include <tiam1808/armv5/am1808/edma_event.h>
 #include <tiam1808/armv5/am1808/evmAM1808.h>
 #include <tiam1808/armv5/am1808/interrupt.h>
+#include <tiam1808/armv5/cp15.h>
 #include <tiam1808/edma.h>
 #include <tiam1808/hw/hw_edma3cc.h>
 #include <tiam1808/hw/hw_syscfg0_AM1808.h>
@@ -54,6 +55,7 @@
 
 #include <umm_malloc.h>
 
+#include <pbdrv/compiler.h>
 #include <pbdrv/ioport.h>
 #include <pbio/port_interface.h>
 
@@ -483,6 +485,13 @@ void ev3_panic_handler(int except_type, ev3_panic_ctx *except_data) {
     panic_puts("\r\nSPSR: 0x");
     panic_putu32(except_data->spsr);
 
+    panic_puts("\r\nDFSR: 0x");
+    panic_putu32(CP15GetDFSR());
+    panic_puts("\r\nIFSR: 0x");
+    panic_putu32(CP15GetIFSR());
+    panic_puts("\r\nFAR: 0x");
+    panic_putu32(CP15GetFAR());
+
     panic_puts("\r\nSystem will now reboot...\r\n");
 
     // Poke the watchdog timer with a bad value to immediately trigger it
@@ -627,6 +636,73 @@ static void Edma3CCErrHandlerIsr(void) {
     }
 }
 
+#define MMU_SECTION_SHIFT   20
+#define MMU_SECTION_SZ      (1 << MMU_SECTION_SHIFT)
+#define MMU_L1_ENTS         (1 << (32 - 20))
+#define MMU_L1_ALIGN        (16 * 1024)
+#define MMU_L1_SECTION(addr, ap, domain, c, b)      (       \
+    ((addr) & ~(MMU_SECTION_SZ - 1)) |                      \
+    (((ap) & 3) << 10) |                                    \
+    (((domain) & 0xf) << 5) |                               \
+    (1 << 4) |                                              \
+    ((!!(c)) << 3) |                                        \
+    ((!!(b)) << 2) |                                        \
+    (1 << 1)                                                \
+    )
+static uint32_t l1_page_table[MMU_L1_ENTS] __attribute__((aligned(MMU_L1_ALIGN)));
+#define SYSTEM_RAM_SZ_MB    64
+
+static void mmu_init(void) {
+    // Invalidate TLB
+    CP15InvTLB();
+
+    // Program domain D0 = no access, D1 = manager (no permission checks)
+    // We generally don't bother with permission checks, anything valid is RWX
+    CP15DomainAccessSet(0b1100);
+
+    // For simplicity, everything is mapped as sections (1 MiB chunks)
+    // This potentially fails to catch certain out-of-bounds accesses,
+    // but as a tradeoff we do not need any L2 sections.
+
+    // MMIO register ranges
+    l1_page_table[0x01C00000 >> MMU_SECTION_SHIFT] = MMU_L1_SECTION(0x01C00000, 0, 1, 0, 0);
+    l1_page_table[0x01D00000 >> MMU_SECTION_SHIFT] = MMU_L1_SECTION(0x01D00000, 0, 1, 0, 0);
+    l1_page_table[0x01E00000 >> MMU_SECTION_SHIFT] = MMU_L1_SECTION(0x01E00000, 0, 1, 0, 0);
+    l1_page_table[0x01F00000 >> MMU_SECTION_SHIFT] = MMU_L1_SECTION(0x01F00000, 0, 1, 0, 0);
+
+    // On-chip RAM, which is used to share control structures with the PRUs
+    l1_page_table[0x80000000 >> MMU_SECTION_SHIFT] = MMU_L1_SECTION(0x80000000, 0, 1, 0, 0);
+
+    // Off-chip main DDR RAM
+    for (unsigned int i = 0; i < SYSTEM_RAM_SZ_MB; i++) {
+        uint32_t addr = 0xC0000000 + i * MMU_SECTION_SZ;
+        // TODO: Enable caching once DMA code is upgraded to handle cache
+        l1_page_table[addr >> MMU_SECTION_SHIFT] = MMU_L1_SECTION(addr, 0, 1, 0, 0);
+    }
+    // Off-chip main DDR RAM, uncacheable mirror @ 0xD0000000
+    for (unsigned int i = 0; i < SYSTEM_RAM_SZ_MB; i++) {
+        uint32_t addr_phys = 0xC0000000 + i * MMU_SECTION_SZ;
+        uint32_t addr_virt = 0xD0000000 + i * MMU_SECTION_SZ;
+        l1_page_table[addr_virt >> MMU_SECTION_SHIFT] = MMU_L1_SECTION(addr_phys, 0, 1, 0, 0);
+    }
+
+    // ARM local RAM, interrupt controller
+    l1_page_table[0xFFF00000 >> MMU_SECTION_SHIFT] = MMU_L1_SECTION(0xFFF00000, 0, 1, 0, 0);
+
+    // Make sure this all makes its way into memory
+    pbdrv_compiler_memory_barrier();
+
+    // Set TTBR
+    CP15TtbSet((uint32_t)l1_page_table);
+
+    uint32_t c15_control = CP15ControlGet();
+    // Clear R and S protection bits (even though we don't use them)
+    c15_control &= ~((1 << 9) | (1 << 8));
+    // Enable I-cache, D-cache, alignment faults, and MMU
+    c15_control |= (1 << 12) | (1 << 2) | (1 << 1) | (1 << 0);
+    CP15ControlSet(c15_control);
+}
+
 enum {
     BOOT_EEPROM_I2C_ADDRESS = 0x50,
 };
@@ -637,6 +713,7 @@ uint8_t pbdrv_ev3_bluetooth_mac_address[6];
 // initialization (low level in pbdrv, high level in pbio), and system level
 // functions for running user code (currently a hardcoded MicroPython script).
 void SystemInit(void) {
+    mmu_init();
 
     SysCfgRegistersUnlock();
 

lib/tiam1808/system_config/armv5/gcc/cp15.c

@@ -37,6 +37,8 @@
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
+#include <stdint.h>
+
 /******************************************************************************
 **                   FUNCTION DEFINITIONS
 ******************************************************************************/
@@ -218,21 +220,10 @@ void CP15DCacheCleanBuff(unsigned int bufPtr, unsigned int size)
  **/
 void CP15TtbSet(unsigned int ttb)
 {
-   /* Invalidates all TLBs.Domain access is selected as
-    * client by configuring domain access register,
-    * in that case access controlled by permission value
-    * set by page table entry
-    */
-    __asm("   mov r1, #0\n\t"
-          "   mcr p15, #0, r1, c8, c7, #0\n\t"
-          "   ldr r1, =0x55555555\n\t"
-          "   mcr p15, #0, r1, c3, c0, #0\n\t");
-
    /* sets translation table base resgister with page table
     * starting address.
     */
     __asm("   mcr p15, #0, %[value], c2, c0, 0":: [value] "r" (ttb));
-
 }
 
 /**
@@ -268,4 +259,64 @@ void CP15MMUEnable(void)
           "    mcr p15, #0, r0, c1, c0, #0\n\t");
 }
 
+/**
+ * \brief   This function gets the data fault status register
+ */
+uint32_t CP15GetDFSR(void)
+{
+    uint32_t ret;
+    __asm("mrc p15, 0, %0, c5, c0, 0" : "=r" (ret));
+    return ret;
+}
+
+/**
+ * \brief   This function gets the instruction fault status register
+ */
+uint32_t CP15GetIFSR(void)
+{
+    uint32_t ret;
+    __asm("mrc p15, 0, %0, c5, c0, 1" : "=r" (ret));
+    return ret;
+}
+
+/**
+ * \brief   This function gets the fault address register
+ */
+uint32_t CP15GetFAR(void)
+{
+    uint32_t ret;
+    __asm("mrc p15, 0, %0, c6, c0, 0" : "=r" (ret));
+    return ret;
+}
+
+/**
+ * \brief   This function invalidates the TLB
+ */
+void CP15InvTLB(void)
+{
+    __asm("   mov r0, #0\n\t"
+          "   mcr p15, #0, r0, c8, c7, #0"
+          ::: "r0");
+}
+
+/**
+ * \brief   This function programs the domain access control register
+ */
+void CP15DomainAccessSet(uint32_t domains)
+{
+    __asm("mcr p15, 0, %0, c3, c0, 0" :: "r"(domains));
+}
+
+uint32_t CP15ControlGet(void)
+{
+    uint32_t ret;
+    __asm("mrc p15, 0, %0, c1, c0, 0" : "=r" (ret));
+    return ret;
+}
+
+void CP15ControlSet(uint32_t control)
+{
+    __asm("mcr p15, 0, %0, c1, c0, 0" :: "r" (control));
+}
+
 /********************************* End Of File *******************************/

lib/tiam1808/tiam1808/armv5/cp15.h

@@ -41,6 +41,8 @@
 #ifndef __CP15_H
 #define __CP15_H
 
+#include <stdint.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -60,6 +62,13 @@ extern void CP15MMUDisable(void);
 extern void CP15MMUEnable(void);
 extern void CP15ICacheFlushBuff(unsigned int ptr, unsigned int size);
 extern void CP15DCacheCleanBuff(unsigned int bufPtr, unsigned int size);
+extern uint32_t CP15GetDFSR(void);
+extern uint32_t CP15GetIFSR(void);
+extern uint32_t CP15GetFAR(void);
+extern void CP15InvTLB(void);
+extern void CP15DomainAccessSet(uint32_t domains);
+extern uint32_t CP15ControlGet(void);
+extern void CP15ControlSet(uint32_t control);
 
 #ifdef __cplusplus
 }