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laurensvalklaurensvalk
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pbio/os: Use namespace for macros.
This makes the invocations a bit longer to fit, but it is probably clearer in the long run. While we are at it, cut one level of abstraction and specify macros in terms of the switch statement directly. Also, instead of LC (contiki), use the terminology "checkpoint", which is untuitive and also technically quite close to reality
1 parent b3717be commit fce8d73

14 files changed

Lines changed: 232 additions & 219 deletions

‎lib/pbio/drv/charger/charger_mp2639a.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -182,17 +182,17 @@ pbio_error_t pbdrv_charger_mp2639a_process_thread(pbio_os_state_t *state, void *
182182

183183
static pbio_os_timer_t timer;
184184

185-
ASYNC_BEGIN(state);
185+
PBIO_OS_ASYNC_BEGIN(state);
186186

187187
#if PBDRV_CONFIG_CHARGER_MP2639A_MODE_PWM
188188
while (pbdrv_pwm_get_dev(platform.mode_pwm_id, &mode_pwm) != PBIO_SUCCESS) {
189-
AWAIT_ONCE(state);
189+
PBIO_OS_AWAIT_ONCE_AND_POLL(state);
190190
}
191191
#endif
192192

193193
#if PBDRV_CONFIG_CHARGER_MP2639A_ISET_PWM
194194
while (pbdrv_pwm_get_dev(platform.iset_pwm_id, &iset_pwm) != PBIO_SUCCESS) {
195-
AWAIT_ONCE(state);
195+
PBIO_OS_AWAIT_ONCE_AND_POLL(state);
196196
}
197197
#endif
198198

@@ -214,7 +214,7 @@ pbio_error_t pbdrv_charger_mp2639a_process_thread(pbio_os_state_t *state, void *
214214
static uint32_t charge_count = 0;
215215

216216
for (;;) {
217-
AWAIT_MS(state, &timer, PBDRV_CHARGER_MP2639A_STATUS_SAMPLE_TIME);
217+
PBIO_OS_AWAIT_MS(state, &timer, PBDRV_CHARGER_MP2639A_STATUS_SAMPLE_TIME);
218218

219219
// Enable charger chip based on USB state. We don't need to disable it
220220
// on charger fault since the chip will automatically disable itself.
@@ -272,12 +272,12 @@ pbio_error_t pbdrv_charger_mp2639a_process_thread(pbio_os_state_t *state, void *
272272
if (charge_count > (PBDRV_CHARGER_MP2639A_CHARGE_TIMEOUT_MS / PBDRV_CHARGER_MP2639A_STATUS_SAMPLE_TIME)) {
273273
pbdrv_charger_status = PBDRV_CHARGER_STATUS_DISCHARGE;
274274
pbdrv_charger_enable(false, PBDRV_CHARGER_LIMIT_NONE);
275-
AWAIT_MS(state, &timer, PBDRV_CHARGER_MP2639A_CHARGE_PAUSE_MS);
275+
PBIO_OS_AWAIT_MS(state, &timer, PBDRV_CHARGER_MP2639A_CHARGE_PAUSE_MS);
276276
charge_count = 0;
277277
}
278278
}
279279

280-
ASYNC_END(PBIO_SUCCESS);
280+
PBIO_OS_ASYNC_END(PBIO_SUCCESS);
281281
}
282282

283283
void pbdrv_charger_init(void) {

‎lib/pbio/drv/pwm/pwm_lp50xx_stm32.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -119,10 +119,10 @@ static pbio_error_t pbdrv_pwm_lp50xx_stm32_process_thread(pbio_os_state_t *state
119119

120120
pbdrv_pwm_lp50xx_stm32_priv_t *priv = context;
121121

122-
ASYNC_BEGIN(state);
122+
PBIO_OS_ASYNC_BEGIN(state);
123123

124124
// Need to allow all drivers to init first.
125-
AWAIT_ONCE(state);
125+
PBIO_OS_AWAIT_ONCE_AND_POLL(state);
126126

127127
static const struct {
128128
uint8_t reg;
@@ -149,14 +149,14 @@ static pbio_error_t pbdrv_pwm_lp50xx_stm32_process_thread(pbio_os_state_t *state
149149
};
150150

151151
HAL_FMPI2C_Master_Transmit_DMA(&priv->hfmpi2c, I2C_ADDR, (void *)&init_data, sizeof(init_data));
152-
AWAIT_UNTIL(state, HAL_FMPI2C_GetState(&priv->hfmpi2c) == HAL_FMPI2C_STATE_READY);
152+
PBIO_OS_AWAIT_UNTIL(state, HAL_FMPI2C_GetState(&priv->hfmpi2c) == HAL_FMPI2C_STATE_READY);
153153

154154
// initialization is finished so consumers can use this PWM device now.
155155
priv->pwm->funcs = &pbdrv_pwm_lp50xx_stm32_funcs;
156156
pbdrv_init_busy_down();
157157

158158
for (;;) {
159-
AWAIT_UNTIL(state, priv->changed);
159+
PBIO_OS_AWAIT_UNTIL(state, priv->changed);
160160

161161
static struct {
162162
uint8_t reg;
@@ -168,11 +168,11 @@ static pbio_error_t pbdrv_pwm_lp50xx_stm32_process_thread(pbio_os_state_t *state
168168
memcpy(color_data.values, priv->values, LP50XX_NUM_CH);
169169
HAL_FMPI2C_Master_Transmit_DMA(&priv->hfmpi2c, I2C_ADDR, (void *)&color_data, sizeof(color_data));
170170
priv->changed = false;
171-
AWAIT_UNTIL(state, HAL_FMPI2C_GetState(&priv->hfmpi2c) == HAL_FMPI2C_STATE_READY);
171+
PBIO_OS_AWAIT_UNTIL(state, HAL_FMPI2C_GetState(&priv->hfmpi2c) == HAL_FMPI2C_STATE_READY);
172172
}
173173

174174
// Unreachable.
175-
ASYNC_END(PBIO_ERROR_FAILED);
175+
PBIO_OS_ASYNC_END(PBIO_ERROR_FAILED);
176176
}
177177

178178
void pbdrv_pwm_lp50xx_stm32_init(pbdrv_pwm_dev_t *devs) {

‎lib/pbio/drv/uart/uart_debug_first_port.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -74,21 +74,21 @@ static pbio_error_t pbdrv_uart_debug_process_thread(pbio_os_state_t *state, void
7474
static pbio_error_t err;
7575
static size_t write_size;
7676

77-
ASYNC_BEGIN(state);
77+
PBIO_OS_ASYNC_BEGIN(state);
7878

7979
while (pbdrv_uart_get_instance(0, &debug_uart) != PBIO_SUCCESS) {
80-
AWAIT_ONCE(state);
80+
PBIO_OS_AWAIT_ONCE_AND_POLL(state);
8181
}
8282

8383
pbdrv_uart_set_baud_rate(debug_uart, 115200);
8484

8585
for (;;) {
86-
AWAIT_UNTIL(state, ring_head != ring_tail);
86+
PBIO_OS_AWAIT_UNTIL(state, ring_head != ring_tail);
8787

8888
// Write up to the end of the buffer without wrapping.
8989
size_t end = ring_head > ring_tail ? ring_head: BUF_SIZE;
9090
write_size = end - ring_tail;
91-
AWAIT(state, &child, pbdrv_uart_write(&child, debug_uart, &ring_buf[ring_tail], write_size, 100));
91+
PBIO_OS_AWAIT(state, &child, pbdrv_uart_write(&child, debug_uart, &ring_buf[ring_tail], write_size, 100));
9292
ring_tail = (ring_tail + write_size) % BUF_SIZE;
9393

9494
// Reset on failure.
@@ -105,7 +105,7 @@ static pbio_error_t pbdrv_uart_debug_process_thread(pbio_os_state_t *state, void
105105
}
106106

107107
// Unreachable.
108-
ASYNC_END(PBIO_ERROR_FAILED);
108+
PBIO_OS_ASYNC_END(PBIO_ERROR_FAILED);
109109
}
110110

111111
void pbdrv_uart_debug_init(void) {

‎lib/pbio/drv/uart/uart_ev3.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@ int32_t pbdrv_uart_get_char(pbdrv_uart_dev_t *uart) {
8686

8787
pbio_error_t pbdrv_uart_read(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uint8_t *msg, uint8_t length, uint32_t timeout) {
8888

89-
ASYNC_BEGIN(state);
89+
PBIO_OS_ASYNC_BEGIN(state);
9090

9191
if (uart->read_buf) {
9292
return PBIO_ERROR_BUSY;
@@ -101,7 +101,7 @@ pbio_error_t pbdrv_uart_read(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uin
101101
}
102102

103103
// Await completion or timeout.
104-
AWAIT_UNTIL(state, ({
104+
PBIO_OS_AWAIT_UNTIL(state, ({
105105
// On every re-entry to the async read, drain the ring buffer
106106
// into the current read buffer. This ensures that we use
107107
// all available data if there have been multiple polls since our last
@@ -123,7 +123,7 @@ pbio_error_t pbdrv_uart_read(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uin
123123
return PBIO_ERROR_TIMEDOUT;
124124
}
125125

126-
ASYNC_END(PBIO_SUCCESS);
126+
PBIO_OS_ASYNC_END(PBIO_SUCCESS);
127127
}
128128

129129
/**
@@ -176,7 +176,7 @@ static bool pbdrv_uart_can_write(pbdrv_uart_dev_t *uart) {
176176

177177
pbio_error_t pbdrv_uart_write(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uint8_t *msg, uint8_t length, uint32_t timeout) {
178178

179-
ASYNC_BEGIN(state);
179+
PBIO_OS_ASYNC_BEGIN(state);
180180

181181
// Can only write one thing at once.
182182
if (uart->write_buf) {
@@ -192,7 +192,7 @@ pbio_error_t pbdrv_uart_write(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, ui
192192
}
193193

194194
// Write one byte at a time until all bytes are written.
195-
AWAIT_UNTIL(state, ({
195+
PBIO_OS_AWAIT_UNTIL(state, ({
196196
// Try to write one byte if any are remaining.
197197
if (uart->write_pos < uart->write_length) {
198198
if (pbdrv_uart_try_to_write_byte(uart, uart->write_buf[uart->write_pos])) {
@@ -210,7 +210,7 @@ pbio_error_t pbdrv_uart_write(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, ui
210210
return PBIO_ERROR_TIMEDOUT;
211211
}
212212

213-
ASYNC_END(PBIO_SUCCESS);
213+
PBIO_OS_ASYNC_END(PBIO_SUCCESS);
214214
}
215215

216216
void pbdrv_uart_set_baud_rate(pbdrv_uart_dev_t *uart, uint32_t baud) {

‎lib/pbio/drv/uart/uart_stm32f0.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ pbio_error_t pbdrv_uart_get_instance(uint8_t id, pbdrv_uart_dev_t **uart_dev) {
6363

6464
pbio_error_t pbdrv_uart_read(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uint8_t *msg, uint8_t length, uint32_t timeout) {
6565

66-
ASYNC_BEGIN(state);
66+
PBIO_OS_ASYNC_BEGIN(state);
6767

6868
if (!msg || !length) {
6969
return PBIO_ERROR_INVALID_ARG;
@@ -82,7 +82,7 @@ pbio_error_t pbdrv_uart_read(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uin
8282
}
8383

8484
// Await completion or timeout.
85-
AWAIT_UNTIL(state, ({
85+
PBIO_OS_AWAIT_UNTIL(state, ({
8686
// On every re-entry to the async read, drain the ring buffer
8787
// into the current read buffer. This ensures that we use
8888
// all available data if there have been multiple polls since our last
@@ -101,12 +101,12 @@ pbio_error_t pbdrv_uart_read(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uin
101101
return PBIO_ERROR_TIMEDOUT;
102102
}
103103

104-
ASYNC_END(PBIO_SUCCESS);
104+
PBIO_OS_ASYNC_END(PBIO_SUCCESS);
105105
}
106106

107107
pbio_error_t pbdrv_uart_write(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uint8_t *msg, uint8_t length, uint32_t timeout) {
108108

109-
ASYNC_BEGIN(state);
109+
PBIO_OS_ASYNC_BEGIN(state);
110110

111111
if (!msg || !length) {
112112
return PBIO_ERROR_INVALID_ARG;
@@ -127,7 +127,7 @@ pbio_error_t pbdrv_uart_write(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, ui
127127
uart->USART->CR1 |= USART_CR1_TXEIE;
128128

129129
// Await completion or timeout.
130-
AWAIT_UNTIL(state, uart->tx_buf_index == uart->tx_buf_size || (timeout && pbio_os_timer_is_expired(&uart->tx_timer)));
130+
PBIO_OS_AWAIT_UNTIL(state, uart->tx_buf_index == uart->tx_buf_size || (timeout && pbio_os_timer_is_expired(&uart->tx_timer)));
131131

132132
uart->tx_buf = NULL;
133133

@@ -136,7 +136,7 @@ pbio_error_t pbdrv_uart_write(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, ui
136136
return PBIO_ERROR_TIMEDOUT;
137137
}
138138

139-
ASYNC_END(PBIO_SUCCESS);
139+
PBIO_OS_ASYNC_END(PBIO_SUCCESS);
140140
}
141141

142142
void pbdrv_uart_set_baud_rate(pbdrv_uart_dev_t *uart, uint32_t baud) {

‎lib/pbio/drv/uart/uart_stm32f4_ll_irq.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ pbio_error_t pbdrv_uart_get_instance(uint8_t id, pbdrv_uart_dev_t **uart_dev) {
6868

6969
pbio_error_t pbdrv_uart_read(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uint8_t *msg, uint8_t length, uint32_t timeout) {
7070

71-
ASYNC_BEGIN(state);
71+
PBIO_OS_ASYNC_BEGIN(state);
7272

7373
if (uart->read_buf) {
7474
return PBIO_ERROR_BUSY;
@@ -83,7 +83,7 @@ pbio_error_t pbdrv_uart_read(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uin
8383
}
8484

8585
// Await completion or timeout.
86-
AWAIT_UNTIL(state, ({
86+
PBIO_OS_AWAIT_UNTIL(state, ({
8787
// On every re-entry to the async read, drain the ring buffer
8888
// into the current read buffer. This ensures that we use
8989
// all available data if there have been multiple polls since our last
@@ -105,12 +105,12 @@ pbio_error_t pbdrv_uart_read(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uin
105105
return PBIO_ERROR_TIMEDOUT;
106106
}
107107

108-
ASYNC_END(PBIO_SUCCESS);
108+
PBIO_OS_ASYNC_END(PBIO_SUCCESS);
109109
}
110110

111111
pbio_error_t pbdrv_uart_write(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uint8_t *msg, uint8_t length, uint32_t timeout) {
112112

113-
ASYNC_BEGIN(state);
113+
PBIO_OS_ASYNC_BEGIN(state);
114114

115115
if (uart->write_buf) {
116116
return PBIO_ERROR_BUSY;
@@ -127,7 +127,7 @@ pbio_error_t pbdrv_uart_write(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, ui
127127
LL_USART_EnableIT_TXE(uart->pdata->uart);
128128

129129
// Await completion or timeout.
130-
AWAIT_UNTIL(state, uart->write_pos == uart->write_length || (timeout && pbio_os_timer_is_expired(&uart->write_timer)));
130+
PBIO_OS_AWAIT_UNTIL(state, uart->write_pos == uart->write_length || (timeout && pbio_os_timer_is_expired(&uart->write_timer)));
131131

132132
uart->write_buf = NULL;
133133

@@ -138,7 +138,7 @@ pbio_error_t pbdrv_uart_write(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, ui
138138
return PBIO_ERROR_TIMEDOUT;
139139
}
140140

141-
ASYNC_END(PBIO_SUCCESS);
141+
PBIO_OS_ASYNC_END(PBIO_SUCCESS);
142142
}
143143

144144
void pbdrv_uart_set_baud_rate(pbdrv_uart_dev_t *uart, uint32_t baud) {

‎lib/pbio/drv/uart/uart_stm32l4_ll_dma.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,7 @@ static uint32_t pbdrv_uart_get_num_available(pbdrv_uart_dev_t *uart) {
190190

191191
pbio_error_t pbdrv_uart_read(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uint8_t *msg, uint8_t length, uint32_t timeout) {
192192

193-
ASYNC_BEGIN(state);
193+
PBIO_OS_ASYNC_BEGIN(state);
194194

195195
if (uart->read_buf) {
196196
return PBIO_ERROR_BUSY;
@@ -205,7 +205,7 @@ pbio_error_t pbdrv_uart_read(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uin
205205

206206
// Wait until we have enough data or timeout. If there is enough data
207207
// already, this completes right away without yielding once first.
208-
AWAIT_UNTIL(state, pbdrv_uart_get_num_available(uart) >= uart->read_length || (timeout && pbio_os_timer_is_expired(&uart->rx_timer)));
208+
PBIO_OS_AWAIT_UNTIL(state, pbdrv_uart_get_num_available(uart) >= uart->read_length || (timeout && pbio_os_timer_is_expired(&uart->rx_timer)));
209209
if (timeout && pbio_os_timer_is_expired(&uart->rx_timer)) {
210210
uart->read_buf = NULL;
211211
uart->read_length = 0;
@@ -225,14 +225,14 @@ pbio_error_t pbdrv_uart_read(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uin
225225
uart->read_buf = NULL;
226226
uart->read_length = 0;
227227

228-
ASYNC_END(PBIO_SUCCESS);
228+
PBIO_OS_ASYNC_END(PBIO_SUCCESS);
229229
}
230230

231231
pbio_error_t pbdrv_uart_write(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, uint8_t *msg, uint8_t length, uint32_t timeout) {
232232

233233
const pbdrv_uart_stm32l4_ll_dma_platform_data_t *pdata = uart->pdata;
234234

235-
ASYNC_BEGIN(state);
235+
PBIO_OS_ASYNC_BEGIN(state);
236236

237237
if (LL_USART_IsEnabledDMAReq_TX(pdata->uart)) {
238238
return PBIO_ERROR_BUSY;
@@ -252,13 +252,13 @@ pbio_error_t pbdrv_uart_write(pbio_os_state_t *state, pbdrv_uart_dev_t *uart, ui
252252
pbio_os_timer_set(&uart->tx_timer, timeout);
253253
}
254254

255-
AWAIT_WHILE(state, LL_USART_IsEnabledDMAReq_TX(pdata->uart) && !(timeout && pbio_os_timer_is_expired(&uart->tx_timer)));
255+
PBIO_OS_AWAIT_WHILE(state, LL_USART_IsEnabledDMAReq_TX(pdata->uart) && !(timeout && pbio_os_timer_is_expired(&uart->tx_timer)));
256256
if ((timeout && pbio_os_timer_is_expired(&uart->tx_timer))) {
257257
LL_USART_DisableDMAReq_TX(pdata->uart);
258258
return PBIO_ERROR_TIMEDOUT;
259259
}
260260

261-
ASYNC_END(PBIO_SUCCESS);
261+
PBIO_OS_ASYNC_END(PBIO_SUCCESS);
262262
}
263263

264264
void pbdrv_uart_set_baud_rate(pbdrv_uart_dev_t *uart, uint32_t baud) {

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