Handle inheritance between multiple processors

[jnkr-ifx]

The previous implementation of ProcessorsBuilder::merge could only handle cases where the parent declared exactly one processor. Handle more complex inheritance patterns, as allowed by the spec:

The element can occur on various levels. The attributes add-up over the different levels (family -> subFamily -> device). Elements of multi-processor devices can be associated with a specific processor using the attribute <Pname>. If the information is relevant to all processors, no processor must be specified in <Pname>.

This is implemented by:

• Adding processors defined in parent elements to child elements.
• Merging attributes into child processors from any parent processors with the same name (or no name at all).
• Filtering out unnamed processor elements at the end.

[mathias-arm]

Could you point to some examples in CMSIS Packs that exercise those new features?

[jnkr-ifx]

I needed this to parse the PSOC Edge CMSIS pack, which defines processors at the family level:

<devices>
  <!-- PSOCE84 -->
  <family Dfamily="PSOCE84" Dvendor="Infineon:7">
    <processor Pname="Cortex-M33" Dcore="Cortex-M33" DcoreVersion="r1p0" Dfpu="SP_FPU" Dmpu="MPU" Dtz="TZ" Ddsp="DSP" Dendian="Little-endian" />
    <processor Pname="Cortex-M55" Dcore="Cortex-M55" DcoreVersion="r1p1" Dfpu="DP_FPU" Dmpu="NO_MPU" Dtz="NO_TZ" Ddsp="DSP" Dmve="FP_MVE" Dendian="Little-endian" />
    <!-- ... -->
    <!-- PSE8xxGMx2xxxx3, 320MHz Max frequency, EPC2 -->
    <subFamily DsubFamily="PSE8xxGMx2xxxx3">
      <processor Pname="Cortex-M33" Dclock="160000000" />
      <processor Pname="Cortex-M55" Dclock="320000000" />
      <memory name="IROM1" access="rxn" start="0x22011000" size="0x59000" default="0" />
      <memory name="IROM2" access="rxs" start="0x32011000" size="0x59000" default="1" alias="IROM1" startup="1" />
      <algorithm Pname="Cortex-M33" name="Flash/PSE84_RRAM_NVM.FLM" start="0x22011000" size="0x59000" RAMstart="0x34008100" RAMsize="0x20000" default="1" style="Keil" />
      <algorithm Pname="Cortex-M33" name="Flash/PSE84_RRAM_NVM_S.FLM" start="0x32011000" size="0x59000" default="1" style="Keil" />
      <algorithm Pname="Cortex-M33" name="Flash/PSE84_SMIF.FLM" start="0x60000000" size="0x4000000" default="0" style="Keil" />
      <algorithm Pname="Cortex-M33" name="Flash/PSE84_SMIF_S.FLM" start="0x70000000" size="0x4000000" default="0" style="Keil" />
      <device Dname="PSE813GMS2DBZQ3B">
        <compile define="PSE813GMS2DBZQ3B" />
      </device>
      <device Dname="PSE823GMS2DBZQ3B">
        <compile define="PSE823GMS2DBZQ3B" />
      </device>
      <device Dname="PSE833GMS2DBZQ3B">
        <compile define="PSE833GMS2DBZQ3B" />
      </device>
    </subFamily>
    <!-- ... -->
  </family>
  <!-- ... -->
</devices>