Cortex-M backend: enable Cortex-M0+ builds against Corstone-300 (#19731)

### Summary 
Extend the Cortex-M cross-CPU build pipeline to Armv6-M by patching two
upstream issues that block the Corstone-300 target source and the CMSIS
Cortex DFP from building for `cortex-m0plus`:

* `core_platform/0003-*.patch` guards the `HardFault_Handler` in
`targets/corstone-300/target.cpp`. The handler uses an `ite eq` IT-block
in inline asm and dereferences the SCB CFSR/BFAR/MMFAR fault-status
registers; both are Armv7-M / Armv8-M Mainline only. The patch wraps the
rich handler in `__ARM_ARCH_7M__ / 7EM / 8M_MAIN / 8_1M_MAIN` and falls
back to a minimal stub on Armv6-M / Armv8-M Baseline (M0/M0+/M23).

* `core_software/0002-*.patch` fixes `cmsis.cmake`'s handling of the M0+
device. The Cortex DFP names the device directory and headers
`ARMCM0plus` (lowercase suffix), while the device sources
(`startup_ARMCM0plus.c`, `system_ARMCM0plus.c`) gate their
implementations on the `ARMCM0P` preprocessor macro — three different
spellings. The previous `string(TOUPPER ...)` produced `ARMCM0PLUS`: the
include path lookup failed and the source files hit their `#error device
not specified!` guard. Override `ARM_CPU` to `ARMCM0plus` for the
directory + filename and introduce a separate `CMSIS_DEVICE_CPU_DEFINE`
set to `ARMCM0P` for the cmsis_startup and cmsis_system
compile-definitions; all other cores still drive both paths from the
uppercased default.

Both patches are layered via the existing `patch_repo` mechanism; the
`corstone_utils.cmake` TODO is updated so the deletion plan for 0002 and
0003 is documented together.

### Test Plan
Locally validated end-to-end on the Corstone-300 FVP with the `qadd`
model: `cortex-m0plus` build links a runner that includes
`startup_ARMCM0plus.c` / `system_ARMCM0plus.c` and the patched
`target.cpp`, and the FVP run prints
`TEST: BundleIO index[0] Test_result: PASS` with all error stats zero.
The bundled `libcmsis-nn.a` reports `Tag_CPU_arch: v6S-M` and
`Tag_THUMB_ISA_use: Thumb-1` with zero DSP / MVE / saturating
instructions, confirming the scalar code path was exercised.

Authored with Claude.

cc @digantdesai @freddan80 @per @zingo @oscarandersson8218 @mansnils
@Sebastian-Larsson @robell

Author: rascani

backends/arm/scripts/corstone_utils.cmake

@@ -50,11 +50,12 @@ function(fetch_ethos_u_content ETHOS_SDK_PATH ET_DIR_PATH)
     WORKING_DIRECTORY ${ET_DIR_PATH}
   )
   # Always patch the core_platform repo since this is fast enough. TODO:
-  # examples/arm/ethos-u-setup/core_platform/0002-*.patch is a transient bridge
-  # that guards Armv8-M-only MPU init so the source compiles for non-Armv8-M
-  # Cortex-M cores. Once the same guard lands upstream in ethos-u/core_platform
-  # and ${core_platform_base_rev} is bumped past that commit, delete the 0002
-  # patch.
+  # examples/arm/ethos-u-setup/core_platform/0002-*.patch and 0003-*.patch are
+  # transient bridges that guard Armv8-M-only MPU init and the Armv7-M-and-newer
+  # HardFault handler so the Corstone-300 target source compiles for older
+  # Cortex-M cores. Once the equivalent guards land upstream in
+  # ethos-u/core_platform and ${core_platform_base_rev} is bumped past those
+  # commits, delete the 0002 and 0003 patches.
   set(core_platform_base_rev "26.02")
   execute_process(
     COMMAND

examples/arm/ethos-u-setup/core_platform/0003-Guard-HardFault-Handler-for-Armv6-M.patch

@@ -0,0 +1,49 @@
+From 380045853a133f298cee1bcf0c959b93ea94f9a2 Mon Sep 17 00:00:00 2001
+From: RJ Ascani <rja@meta.com>
+Date: Wed, 13 May 2026 15:42:13 -0700
+Subject: [PATCH] Guard HardFault_Handler for Armv6-M / Armv8-M Baseline
+
+The Corstone-300 HardFault_Handler is written for Armv7-M / Armv8-M
+Mainline: it uses an `ite eq` IT-block in inline asm, and dereferences
+the SCB CFSR/BFAR/MMFAR fault-status registers. Neither is available
+on Armv6-M (Cortex-M0/M0+) or Armv8-M Baseline (Cortex-M23), so the
+file fails to compile when the Corstone-300 target source is built
+with `-mcpu=cortex-m0plus` to exercise the scalar CMSIS-NN code paths
+on the Corstone-300 M55 simulator (an ISA superset).
+
+Wrap the Mainline-only implementation in
+`__ARM_ARCH_7M__ / 7EM / 8M_MAIN / 8_1M_MAIN` and fall back to a
+minimal `printf("Hard fault"); exit(1)` stub on Baseline cores.
+---
+ targets/corstone-300/target.cpp | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/targets/corstone-300/target.cpp b/targets/corstone-300/target.cpp
+index bda2248..4aa3eea 100644
+--- a/targets/corstone-300/target.cpp
++++ b/targets/corstone-300/target.cpp
+@@ -246,6 +246,11 @@ struct ExcContext {
+ };
+ 
+ void HardFault_Handler() {
++    // Armv6-M (M0/M0+) and Armv8-M Baseline (M23) lack the IT instruction and
++    // the SCB CFSR/BFAR/MMFAR fault-status registers, so the rich handler
++    // can't compile or run there. Fall back to a minimal stub on those cores.
++#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || \
++    defined(__ARM_ARCH_8_1M_MAIN__)
+     int irq;
+     struct ExcContext *e;
+     uint32_t sp;
+@@ -267,6 +272,9 @@ void HardFault_Handler() {
+            sp);
+     printf(
+         "%11s cfsr=0x%08" PRIx32 " bfar=0x%08" PRIx32 " mmfar=0x%08" PRIx32 "\n", "", SCB->CFSR, SCB->BFAR, SCB->MMFAR);
++#else
++    printf("Hard fault\n");
++#endif
+     exit(1);
+ }
+ }
+-- 
+2.53.0
+

examples/arm/ethos-u-setup/core_software/0002-Fix-ARMCM0plus-directory-case-and-compile-define-mis.patch

@@ -0,0 +1,77 @@
+From 1ee9cf9c956ea6a266fc79dfa62071131f162510 Mon Sep 17 00:00:00 2001
+From: RJ Ascani <rja@meta.com>
+Date: Wed, 13 May 2026 15:48:07 -0700
+Subject: [PATCH] Fix ARMCM0plus directory case and compile-define mismatch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The Cortex DFP names the Cortex-M0+ device directory and headers
+`ARMCM0plus` (lowercase suffix), while the device source files
+(`startup_ARMCM0plus.c`, `system_ARMCM0plus.c`) gate their
+implementations on the `ARMCM0P` preprocessor macro — three different
+spellings. `cmsis.cmake` previously did
+`string(TOUPPER \"ARMCM\${CPU_NUMBER}\" ARM_CPU)`, producing
+`ARMCM0PLUS`: the include path lookup fails and the source files hit
+their `#error device not specified!` guard.
+
+Override `ARM_CPU` to `ARMCM0plus` and introduce a separate
+`CMSIS_DEVICE_CPU_DEFINE` set to `ARMCM0P` for the cmsis_startup and
+cmsis_system compile-definitions; all other cores still drive both
+paths from the uppercased default.
+---
+ cmsis.cmake | 20 ++++++++++++++++++--
+ 1 file changed, 18 insertions(+), 2 deletions(-)
+
+diff --git a/cmsis.cmake b/cmsis.cmake
+index 7f2b93f..c49f205 100644
+--- a/cmsis.cmake
++++ b/cmsis.cmake
+@@ -23,6 +23,15 @@ endif()
+ 
+ string(TOUPPER "ARMCM${CPU_NUMBER}" ARM_CPU)
+ 
++# Cortex-M0+ is special: the Cortex DFP names the device directory and headers
++# `ARMCM0plus` (lowercase suffix), while the device sources gate their
++# implementations on the `ARMCM0P` preprocessor macro. Override both so the
++# directory lookup and `#include` resolution succeed; the compile-definition
++# override is applied instead of `CMSIS_DEVICE_CPU_FEATURE` further down.
++if(CPU_NUMBER STREQUAL "0plus")
++    set(ARM_CPU "ARMCM0plus")
++endif()
++
+ # Set CPU specific features
+ if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m33(\\+|$)")
+     set(ARM_FEATURES "_DSP_FP")
+@@ -50,6 +59,13 @@ else()
+     cmake_path(SET CMSIS_DEVICE_CPU_FEATURE "${ARM_CPU}")
+ endif()
+ 
++# Macro the device sources gate on. Matches CMSIS_DEVICE_CPU_FEATURE for most
++# cores; Cortex-M0+ keys off `ARMCM0P`, not `ARMCM0plus`.
++set(CMSIS_DEVICE_CPU_DEFINE "${CMSIS_DEVICE_CPU_FEATURE}")
++if(CPU_NUMBER STREQUAL "0plus")
++    set(CMSIS_DEVICE_CPU_DEFINE "ARMCM0P")
++endif()
++
+ target_include_directories(cmsis_device INTERFACE ${CMSIS_DEVICE_PATH}/${ARM_CPU}/Include)
+ 
+ target_compile_options(cmsis_device INTERFACE
+@@ -66,12 +82,12 @@ target_sources(cmsis_startup INTERFACE
+ set_source_files_properties(${CMSIS_DEVICE_PATH}/${ARM_CPU}/Source/startup_${ARM_CPU}.c
+     PROPERTIES COMPILE_FLAGS -Wno-redundant-decls)
+ 
+-target_compile_definitions(cmsis_startup INTERFACE ${CMSIS_DEVICE_CPU_FEATURE})
++target_compile_definitions(cmsis_startup INTERFACE ${CMSIS_DEVICE_CPU_DEFINE})
+ target_link_libraries(cmsis_startup INTERFACE cmsis_device)
+ 
+ # CMSIS system
+ add_library(cmsis_system INTERFACE)
+ target_sources(cmsis_system INTERFACE
+     ${CMSIS_DEVICE_PATH}/${ARM_CPU}/Source/system_${ARM_CPU}.c)
+-target_compile_definitions(cmsis_system INTERFACE ${CMSIS_DEVICE_CPU_FEATURE})
++target_compile_definitions(cmsis_system INTERFACE ${CMSIS_DEVICE_CPU_DEFINE})
+ target_link_libraries(cmsis_system INTERFACE cmsis_startup)
+-- 
+2.53.0
+