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Cortex-M: Thread target CPU/ISA through the AOT pass manager (#19470)
### Summary
Introduce a CortexMCompileConfig dataclass (cpu + isa) that carries
Cortex-M target information from the --target=cortex-m<variant>+int8 CLI
string into CortexMPassManager. The full standard Cortex-M lineup is
registered (M0, M0+, M3, M4, M7, M23, M33, M35P, M52, M55, M85), each
with a sensible default ISA; the optional-DSP M33/M35P and optional-MVE
M52/M55/M85 cases can be expressed via the isa= kwarg.
No pass reads the config yet, so this change is purely plumbing, but it
positions both the upcoming AOT scratch-buffer sizing work (#16580) and
the CMSIS-NN scalar (#17646) / DSP (#17644) backend support to plug in
without re-plumbing the call site. Actually building for the new
variants still requires
CortexMTester gains an optional config kwarg, and the Pico 2 MLP example
now constructs CortexMPassManager with cpu='cortex-m33' to match the
RP2350 hardware it targets.
Authored with Claude.
cc @digantdesai@freddan80@per@zingo@oscarandersson8218@mansnils@Sebastian-Larsson@robell
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