Arm backend: Convert asserts to raise errors in op_mul (#10134)

Asserts are converted to proper raises to ensure graph integrity.

Improve error message.


Signed-off-by: Sebastian Larsson <sebastian.larsson@arm.com>
Co-authored-by: Oscar Andersson <87121123+oscarandersson8218@users.noreply.github.com>

Author: Sebastian-Larsson

backends/arm/operators/op_mul.py

@@ -41,7 +41,15 @@ def define_node(
         inputs: List[TosaArg],
         output: TosaArg,
     ) -> None:
-        assert inputs[0].dtype == inputs[1].dtype == output.dtype == ts.DType.INT8
+        if (
+            inputs[0].dtype != ts.DType.INT8
+            or inputs[1].dtype != ts.DType.INT8
+            or output.dtype != ts.DType.INT8
+        ):
+            raise ValueError(
+                f"Inputs and output for {self.target} need to be INT8, got "
+                f"{inputs[0].dtype=}, {inputs[1].dtype=} and {output.dtype=}"
+            )
 
         dim_order = (
             inputs[0].dim_order