Place model PTE in DDR to fix FVP link-time memory overflow

The MV2 model PTE (~3.5 MB) overflows both the 512 KiB ITCM (FLASH)
and 2 MiB ISRAM (RAM) regions on Corstone-300 FVP, and similarly on
Corstone-320.

Fix: declare a DDR memory region (0x7000_0000, 16 MiB) via DTS overlay
on both FVP boards and route the network_model_sec linker section there
via a Zephyr linker snippet.  A new Kconfig option
ET_ARM_MODEL_PTE_DMA_ACCESSIBLE (enabled for FVP boards) tells main.cpp
to use the model blob in-place instead of memcpy-ing it into a second
SRAM buffer, since the Ethos-U can DMA from DDR on the FVP.

Also adds pool-size overrides for Corstone-320 (previously only had
CONFIG_ETHOS_U=y).

Co-authored-by: Claude <noreply@anthropic.com>

Author: psiddh

zephyr/samples/mv2-ethosu/CMakeLists.txt

@@ -97,6 +97,15 @@ else()
 endif()
 
 find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+dt_nodelabel(model_ddr_path NODELABEL "model_ddr")
+if(model_ddr_path)
+  configure_file(
+    model_section.ld.in ${CMAKE_CURRENT_BINARY_DIR}/model_section.ld @ONLY
+  )
+  zephyr_linker_sources(SECTIONS ${CMAKE_CURRENT_BINARY_DIR}/model_section.ld)
+endif()
+
 project(executorch_mv2_ethosu)
 
 set(CMAKE_CXX_FLAGS
@@ -224,6 +233,9 @@ if(DEFINED CONFIG_EXECUTORCH_TEMP_ALLOCATOR_POOL_SIZE)
       ET_ARM_BAREMETAL_SCRATCH_TEMP_ALLOCATOR_POOL_SIZE=${CONFIG_EXECUTORCH_TEMP_ALLOCATOR_POOL_SIZE}
   )
 endif()
+if(CONFIG_ET_ARM_MODEL_PTE_DMA_ACCESSIBLE)
+  target_compile_definitions(app PRIVATE ET_ARM_MODEL_PTE_DMA_ACCESSIBLE)
+endif()
 
 target_link_libraries(app PRIVATE libexecutorch)
 if(EXECUTORCH_OPS_LIB)

zephyr/samples/mv2-ethosu/Kconfig

@@ -8,6 +8,17 @@ source "Kconfig.zephyr"
 
 menu "ExecuTorch MobileNetV2 sample configuration"
 
+config ET_ARM_MODEL_PTE_DMA_ACCESSIBLE
+	bool "Model PTE is in DMA-accessible memory"
+	default n
+	help
+	  Skip copying the model PTE blob to a separate SRAM buffer at
+	  runtime. Enable this when the embedded model blob already resides
+	  in memory the Ethos-U NPU can DMA from (e.g. DDR on Corstone FVP,
+	  MRAM on Alif). This is independent of where the linker places the
+	  model section; DDR placement is controlled by the model_ddr DTS
+	  node in the board overlay.
+
 config EXECUTORCH_METHOD_ALLOCATOR_POOL_SIZE
 	int "Method allocator pool size in bytes"
 	default 1572864

zephyr/samples/mv2-ethosu/boards/mps3_corstone300_fvp.conf

@@ -8,7 +8,11 @@
 # and use the hardware instance exposed by the board DTS.
 CONFIG_ETHOS_U=y
 
+# Model PTE is placed in DDR via linker snippet; the Ethos-U can DMA from
+# DDR on the FVP so no SRAM copy is needed.
+CONFIG_ET_ARM_MODEL_PTE_DMA_ACCESSIBLE=y
+
 # Corstone-300 has 2 MiB ISRAM. Reduce pool sizes to fit within budget
-# alongside stack, heap, model data, and runtime buffers.
+# alongside stack, heap, and runtime buffers.
 CONFIG_EXECUTORCH_METHOD_ALLOCATOR_POOL_SIZE=786432
 CONFIG_EXECUTORCH_TEMP_ALLOCATOR_POOL_SIZE=786432

zephyr/samples/mv2-ethosu/boards/mps3_corstone300_fvp.overlay

@@ -9,9 +9,19 @@
  * DMA can access. The default board DTS routes Zephyr's general-purpose
  * SRAM to DTCM, which the NPU cannot reach. Override the choice so that
  * .data/.bss land in ISRAM (0x3100_0000) instead.
+ *
+ * The model PTE blob is placed in DDR (0x7000_0000) via a linker snippet
+ * to avoid overflowing the 2 MiB ISRAM and 512 KiB ITCM regions.
+ * The Ethos-U can DMA from DDR on the Corstone-300 FVP.
  */
 / {
 	chosen {
 		zephyr,sram = &isram;
 	};
+
+	model_ddr: memory@70000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x70000000 DT_SIZE_M(16)>;
+		zephyr,memory-region = "MODEL_DDR";
+	};
 };

zephyr/samples/mv2-ethosu/boards/mps4_corstone320_fvp.conf

@@ -7,3 +7,12 @@
 # Enable the Zephyr Ethos-U driver so executorch_delegate_ethos_u can reserve
 # and use the hardware instance exposed by the board DTS.
 CONFIG_ETHOS_U=y
+
+# Model PTE is placed in DDR via linker snippet; the Ethos-U can DMA from
+# DDR on the FVP so no SRAM copy is needed.
+CONFIG_ET_ARM_MODEL_PTE_DMA_ACCESSIBLE=y
+
+# Corstone-320 has 4 MiB SRAM. Reduce pool sizes from the 1.5 MiB defaults
+# to leave headroom for stack, heap, and runtime buffers.
+CONFIG_EXECUTORCH_METHOD_ALLOCATOR_POOL_SIZE=786432
+CONFIG_EXECUTORCH_TEMP_ALLOCATOR_POOL_SIZE=786432

zephyr/samples/mv2-ethosu/boards/mps4_corstone320_fvp.overlay

@@ -0,0 +1,18 @@
+/* Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * Copyright 2026 Arm Limited and/or its affiliates.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* The model PTE blob is placed in DDR (0x7000_0000) via a linker snippet
+ * to avoid overflowing SRAM with the full MobileNetV2 model.
+ * The Ethos-U can DMA from DDR on the Corstone-320 FVP.
+ */
+/ {
+	model_ddr: memory@70000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x70000000 DT_SIZE_M(16)>;
+		zephyr,memory-region = "MODEL_DDR";
+	};
+};

zephyr/samples/mv2-ethosu/model_section.ld.in

@@ -0,0 +1,13 @@
+/* Place the model PTE blob in DDR so it does not overflow the small
+ * ITCM (FLASH) and ISRAM (RAM) regions on Corstone FVP boards.
+ * The Ethos-U NPU can DMA from DDR on these platforms.
+ *
+ * Section name is substituted from the ET_PTE_SECTION CMake variable
+ * so this stays in sync with pte_to_header.py --section.
+ */
+SECTION_DATA_PROLOGUE(@ET_PTE_SECTION@,,)
+{
+    . = ALIGN(16);
+    *(.@ET_PTE_SECTION@)
+    *(.@ET_PTE_SECTION@.*)
+} GROUP_DATA_LINK_IN(MODEL_DDR, MODEL_DDR)