Hoist W4A8 activation quantization out of GEMM K-loop

Add dedicated _quantize_activations_int8_kernel and _silu_quantize_int8_kernel
that pre-quantize activations to INT8 with per-row-per-tile FP32 scales before
GEMM1 and GEMM2 respectively. The existing _fused_moe_batched_int8_kernel and
_fused_moe_silu_batched_int8_kernel are rewritten to consume pre-quantized
activations + scales, eliminating ~256 redundant tl.max reductions per program
(cdiv(K, BLOCK_K) tiles * BLOCK_M rows) and halving activation HBM bandwidth in
the K-loop (bf16 -> int8). BLOCK_SIZE_K is fixed at PREQUANT_BLOCK_K (= 128)
so per-tile activation scales align with the GEMM K-loop.

Correctness: 7/7 microbenchmark configs pass with rel diff <1.5% vs BF16 ref.
End-to-end (Qwen3.5 MoE 1600 prefill + 512 decode, --cuda_graph, A100):
prefill 5727 -> 6171 tok/s (+7.7%), decode 92.6 -> 99.0 tok/s (+6.9%).

Author: Gasoonjia

backends/cuda/tests/test_int4_matmul.py

@@ -19,7 +19,6 @@
 import unittest
 
 import torch
-import torch.nn as nn
 
 from executorch.backends.cuda.triton.kernels.int4_matmul import (
     dequant_w4_to_bf16,

backends/cuda/triton/kernels/__init__.py

@@ -8,6 +8,7 @@
     fused_moe,
     fused_moe_batched,
     fused_moe_batched_gemm,
+    fused_moe_batched_gemm_int8,
     moe_align_block_size,
 )
 
@@ -23,6 +24,8 @@
     "fused_moe",
     "fused_moe_batched",
     "fused_moe_batched_gemm",
+    "fused_moe_batched_gemm_int8",
+    "int4_matvec",
     "moe_align_block_size",
     "sdpa",
     "sdpa_decode_splitk",