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Merge branch 'main' into dynamic_unbound_kv_cache
2 parents 2fd3d18 + 043c404 commit e56b926

3 files changed

Lines changed: 132 additions & 5 deletions

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‎backends/arm/scripts/corstone_utils.cmake‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -50,11 +50,12 @@ function(fetch_ethos_u_content ETHOS_SDK_PATH ET_DIR_PATH)
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WORKING_DIRECTORY ${ET_DIR_PATH}
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)
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# Always patch the core_platform repo since this is fast enough. TODO:
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# examples/arm/ethos-u-setup/core_platform/0002-*.patch is a transient bridge
54-
# that guards Armv8-M-only MPU init so the source compiles for non-Armv8-M
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# Cortex-M cores. Once the same guard lands upstream in ethos-u/core_platform
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# and ${core_platform_base_rev} is bumped past that commit, delete the 0002
57-
# patch.
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# examples/arm/ethos-u-setup/core_platform/0002-*.patch and 0003-*.patch are
54+
# transient bridges that guard Armv8-M-only MPU init and the Armv7-M-and-newer
55+
# HardFault handler so the Corstone-300 target source compiles for older
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# Cortex-M cores. Once the equivalent guards land upstream in
57+
# ethos-u/core_platform and ${core_platform_base_rev} is bumped past those
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# commits, delete the 0002 and 0003 patches.
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set(core_platform_base_rev "26.02")
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execute_process(
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COMMAND

‎examples/arm/ethos-u-setup/core_platform/0003-Guard-HardFault-Handler-for-Armv6-M.patch‎

Lines changed: 49 additions & 0 deletions
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@@ -0,0 +1,49 @@
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From 380045853a133f298cee1bcf0c959b93ea94f9a2 Mon Sep 17 00:00:00 2001
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From: RJ Ascani <rja@meta.com>
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Date: Wed, 13 May 2026 15:42:13 -0700
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Subject: [PATCH] Guard HardFault_Handler for Armv6-M / Armv8-M Baseline
5+
6+
The Corstone-300 HardFault_Handler is written for Armv7-M / Armv8-M
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Mainline: it uses an `ite eq` IT-block in inline asm, and dereferences
8+
the SCB CFSR/BFAR/MMFAR fault-status registers. Neither is available
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on Armv6-M (Cortex-M0/M0+) or Armv8-M Baseline (Cortex-M23), so the
10+
file fails to compile when the Corstone-300 target source is built
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with `-mcpu=cortex-m0plus` to exercise the scalar CMSIS-NN code paths
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on the Corstone-300 M55 simulator (an ISA superset).
13+
14+
Wrap the Mainline-only implementation in
15+
`__ARM_ARCH_7M__ / 7EM / 8M_MAIN / 8_1M_MAIN` and fall back to a
16+
minimal `printf("Hard fault"); exit(1)` stub on Baseline cores.
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---
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targets/corstone-300/target.cpp | 8 ++++++++
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1 file changed, 8 insertions(+)
20+
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diff --git a/targets/corstone-300/target.cpp b/targets/corstone-300/target.cpp
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index bda2248..4aa3eea 100644
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--- a/targets/corstone-300/target.cpp
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+++ b/targets/corstone-300/target.cpp
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@@ -246,6 +246,11 @@ struct ExcContext {
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};
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void HardFault_Handler() {
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+ // Armv6-M (M0/M0+) and Armv8-M Baseline (M23) lack the IT instruction and
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+ // the SCB CFSR/BFAR/MMFAR fault-status registers, so the rich handler
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+ // can't compile or run there. Fall back to a minimal stub on those cores.
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+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || \
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+ defined(__ARM_ARCH_8_1M_MAIN__)
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int irq;
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struct ExcContext *e;
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uint32_t sp;
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@@ -267,6 +272,9 @@ void HardFault_Handler() {
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sp);
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printf(
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"%11s cfsr=0x%08" PRIx32 " bfar=0x%08" PRIx32 " mmfar=0x%08" PRIx32 "\n", "", SCB->CFSR, SCB->BFAR, SCB->MMFAR);
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+#else
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+ printf("Hard fault\n");
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+#endif
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exit(1);
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}
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}
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--
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2.53.0
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‎examples/arm/ethos-u-setup/core_software/0002-Fix-ARMCM0plus-directory-case-and-compile-define-mis.patch‎

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,77 @@
1+
From 1ee9cf9c956ea6a266fc79dfa62071131f162510 Mon Sep 17 00:00:00 2001
2+
From: RJ Ascani <rja@meta.com>
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Date: Wed, 13 May 2026 15:48:07 -0700
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Subject: [PATCH] Fix ARMCM0plus directory case and compile-define mismatch
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The Cortex DFP names the Cortex-M0+ device directory and headers
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`ARMCM0plus` (lowercase suffix), while the device source files
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(`startup_ARMCM0plus.c`, `system_ARMCM0plus.c`) gate their
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implementations on the `ARMCM0P` preprocessor macro — three different
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spellings. `cmsis.cmake` previously did
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`string(TOUPPER \"ARMCM\${CPU_NUMBER}\" ARM_CPU)`, producing
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`ARMCM0PLUS`: the include path lookup fails and the source files hit
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their `#error device not specified!` guard.
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Override `ARM_CPU` to `ARMCM0plus` and introduce a separate
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`CMSIS_DEVICE_CPU_DEFINE` set to `ARMCM0P` for the cmsis_startup and
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cmsis_system compile-definitions; all other cores still drive both
21+
paths from the uppercased default.
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---
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cmsis.cmake | 20 ++++++++++++++++++--
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1 file changed, 18 insertions(+), 2 deletions(-)
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diff --git a/cmsis.cmake b/cmsis.cmake
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index 7f2b93f..c49f205 100644
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--- a/cmsis.cmake
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+++ b/cmsis.cmake
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@@ -23,6 +23,15 @@ endif()
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string(TOUPPER "ARMCM${CPU_NUMBER}" ARM_CPU)
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+# Cortex-M0+ is special: the Cortex DFP names the device directory and headers
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+# `ARMCM0plus` (lowercase suffix), while the device sources gate their
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+# implementations on the `ARMCM0P` preprocessor macro. Override both so the
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+# directory lookup and `#include` resolution succeed; the compile-definition
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+# override is applied instead of `CMSIS_DEVICE_CPU_FEATURE` further down.
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+if(CPU_NUMBER STREQUAL "0plus")
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+ set(ARM_CPU "ARMCM0plus")
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+endif()
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+
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# Set CPU specific features
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if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m33(\\+|$)")
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set(ARM_FEATURES "_DSP_FP")
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@@ -50,6 +59,13 @@ else()
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cmake_path(SET CMSIS_DEVICE_CPU_FEATURE "${ARM_CPU}")
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endif()
49+
50+
+# Macro the device sources gate on. Matches CMSIS_DEVICE_CPU_FEATURE for most
51+
+# cores; Cortex-M0+ keys off `ARMCM0P`, not `ARMCM0plus`.
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+set(CMSIS_DEVICE_CPU_DEFINE "${CMSIS_DEVICE_CPU_FEATURE}")
53+
+if(CPU_NUMBER STREQUAL "0plus")
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+ set(CMSIS_DEVICE_CPU_DEFINE "ARMCM0P")
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+endif()
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+
57+
target_include_directories(cmsis_device INTERFACE ${CMSIS_DEVICE_PATH}/${ARM_CPU}/Include)
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59+
target_compile_options(cmsis_device INTERFACE
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@@ -66,12 +82,12 @@ target_sources(cmsis_startup INTERFACE
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set_source_files_properties(${CMSIS_DEVICE_PATH}/${ARM_CPU}/Source/startup_${ARM_CPU}.c
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PROPERTIES COMPILE_FLAGS -Wno-redundant-decls)
63+
64+
-target_compile_definitions(cmsis_startup INTERFACE ${CMSIS_DEVICE_CPU_FEATURE})
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+target_compile_definitions(cmsis_startup INTERFACE ${CMSIS_DEVICE_CPU_DEFINE})
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target_link_libraries(cmsis_startup INTERFACE cmsis_device)
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# CMSIS system
69+
add_library(cmsis_system INTERFACE)
70+
target_sources(cmsis_system INTERFACE
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${CMSIS_DEVICE_PATH}/${ARM_CPU}/Source/system_${ARM_CPU}.c)
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-target_compile_definitions(cmsis_system INTERFACE ${CMSIS_DEVICE_CPU_FEATURE})
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+target_compile_definitions(cmsis_system INTERFACE ${CMSIS_DEVICE_CPU_DEFINE})
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target_link_libraries(cmsis_system INTERFACE cmsis_startup)
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--
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2.53.0
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