[ET-VK][ez] Add AOT support for PackedInt8_4C1W dtype#17389
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meta-codesync[bot] merged 8 commits intogh/SS-JIA/420/basefrom Feb 13, 2026
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[ET-VK][ez] Add AOT support for PackedInt8_4C1W dtype#17389meta-codesync[bot] merged 8 commits intogh/SS-JIA/420/basefrom
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This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/) [ghstack-poisoned]
🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/17389
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This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/) [ghstack-poisoned]
This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/) [ghstack-poisoned]
This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/) [ghstack-poisoned]
This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/) [ghstack-poisoned]
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This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/) [ghstack-poisoned]
This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/) [ghstack-poisoned]
This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/) [ghstack-poisoned]
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Pull Request resolved: #17389 This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) ghstack-source-id: 340983070 @exported-using-ghexport Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/)
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Pull Request resolved: #17389 This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) ghstack-source-id: 340983070 @exported-using-ghexport Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/)
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Pull Request resolved: #17389 This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) ghstack-source-id: 340983070 @exported-using-ghexport Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/)
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Pull Request resolved: #17389 This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) ghstack-source-id: 340983070 @exported-using-ghexport Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/)
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Pull Request resolved: #17389 This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) ghstack-source-id: 340983070 @exported-using-ghexport Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/)
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Pull Request resolved: pytorch#17389 This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results. - Adds PACKED_INT8_4C1W = 8 to the FlatBuffers schema and Python schema class - Adds deserialization mapping in VulkanBackend.cpp - Updates quantize/dequantize per-tensor op registrations to accept any PackedInt8 layout (not just 4W4C), enabling the layout propagation pass to choose the optimal layout - Adds new TensorRepSet constants: PACKED_INT8_BUFFER (all quantized layouts), PACKED_INT8_4C1W_BUFFER, and PACKED_INT8_CHANNELS_PACKED_BUFFER (4W4C + 4C1W) ghstack-source-id: 340983070 @exported-using-ghexport Differential Revision: [D93000167](https://our.internmc.facebook.com/intern/diff/D93000167/)
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Stack from ghstack (oldest at bottom):
This adds end-to-end support for the PackedInt8_4C1W memory layout throughout the serialization and AOT pipeline. The 4C1W layout packs 4 channels into a single texel with width-major ordering, which is the natural output layout for convolutions that produce channel-packed results.
Differential Revision: D93000167