Fix SLEEF preprocessor macro name to match ATen vec headers#18645
Fix SLEEF preprocessor macro name to match ATen vec headers#18645kimishpatel wants to merge 4 commits intogh/kimishpatel/218/basefrom
Conversation
The ATen NEON vectorized math headers (vec128_float_neon.h) check for AT_BUILD_ARM_VEC256_WITH_SLEEF to enable SLEEF intrinsics for exp(), log(), etc. ExecuTorch's get_vec_preprocessor_flags() was defining ET_BUILD_ARM_VEC256_WITH_SLEEF (wrong prefix), so the USE_SLEEF macro always took the fallback path: map(std::exp) — scalar exp called per-element with full vector load/store overhead wrapping it. With this fix, Vectorized<float>::exp() correctly dispatches to Sleef_expf4_u10 on ARM, which is the intended behavior. Differential Revision: [D96044314](https://our.internmc.facebook.com/intern/diff/D96044314/) [ghstack-poisoned]
🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/18645
Note: Links to docs will display an error until the docs builds have been completed. ❌ 1 New Failure, 1 Cancelled Job, 3 Pending, 2 Unrelated FailuresAs of commit 18aed0f with merge base 4afd7f9 ( NEW FAILURE - The following job has failed:
CANCELLED JOB - The following job was cancelled. Please retry:
BROKEN TRUNK - The following jobs failed but were present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
This comment was automatically generated by Dr. CI and updates every 15 minutes. |
This PR needs a
|
digantdesai
left a comment
There was a problem hiding this comment.
Review automatically exported from Phabricator review in Meta.
The ATen NEON vectorized math headers (vec128_float_neon.h) check for AT_BUILD_ARM_VEC256_WITH_SLEEF to enable SLEEF intrinsics for exp(), log(), etc. ExecuTorch's get_vec_preprocessor_flags() was defining ET_BUILD_ARM_VEC256_WITH_SLEEF (wrong prefix), so the USE_SLEEF macro always took the fallback path: map(std::exp) — scalar exp called per-element with full vector load/store overhead wrapping it. With this fix, Vectorized<float>::exp() correctly dispatches to Sleef_expf4_u10 on ARM, which is the intended behavior. Differential Revision: [D96044314](https://our.internmc.facebook.com/intern/diff/D96044314/) [ghstack-poisoned]
The ATen NEON vectorized math headers (vec128_float_neon.h) check for AT_BUILD_ARM_VEC256_WITH_SLEEF to enable SLEEF intrinsics for exp(), log(), etc. ExecuTorch's get_vec_preprocessor_flags() was defining ET_BUILD_ARM_VEC256_WITH_SLEEF (wrong prefix), so the USE_SLEEF macro always took the fallback path: map(std::exp) — scalar exp called per-element with full vector load/store overhead wrapping it. With this fix, Vectorized<float>::exp() correctly dispatches to Sleef_expf4_u10 on ARM, which is the intended behavior. Differential Revision: [D96044314](https://our.internmc.facebook.com/intern/diff/D96044314/) [ghstack-poisoned]
The ATen NEON vectorized math headers (vec128_float_neon.h) check for AT_BUILD_ARM_VEC256_WITH_SLEEF to enable SLEEF intrinsics for exp(), log(), etc. ExecuTorch's get_vec_preprocessor_flags() was defining ET_BUILD_ARM_VEC256_WITH_SLEEF (wrong prefix), so the USE_SLEEF macro always took the fallback path: map(std::exp) — scalar exp called per-element with full vector load/store overhead wrapping it. With this fix, Vectorized<float>::exp() correctly dispatches to Sleef_expf4_u10 on ARM, which is the intended behavior. Differential Revision: [D96044314](https://our.internmc.facebook.com/intern/diff/D96044314/) [ghstack-poisoned]
Stack from ghstack (oldest at bottom):
The ATen NEON vectorized math headers (vec128_float_neon.h) check for
AT_BUILD_ARM_VEC256_WITH_SLEEF to enable SLEEF intrinsics for exp(),
log(), etc. ExecuTorch's get_vec_preprocessor_flags() was defining
ET_BUILD_ARM_VEC256_WITH_SLEEF (wrong prefix), so the USE_SLEEF macro
always took the fallback path: map(std::exp) — scalar exp called
per-element with full vector load/store overhead wrapping it.
With this fix, Vectorized::exp() correctly dispatches to
Sleef_expf4_u10 on ARM, which is the intended behavior.
Differential Revision: D96044314