[ET-VK][sdpa] Add SDPA operator perf benchmark binary (test_sdpa)#21116
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Pull Request resolved: #21062 Adds a standalone custom-ops perf binary that builds a ComputeGraph containing only the SDPA op (`llama.custom_sdpa`, the causal LLM KV-cache decode/prefill path) and reports per-dispatch GPU timing for the three SDPA dispatches (QK GEMM, softmax, AV GEMM) in isolation, so shader variants can be A/B-benchmarked without a full model. `TestSDPA.cpp` registers a `test_etvk.test_sdpa` op wrapper that synthesizes `input_pos` from the tensor shapes and drives `llama.custom_sdpa`. Two env toggles: `SDPA_DECODE_ONLY=1` restricts the sweep to the decode (S==1) shape matrix, and `SDPA_NO_CHAIN=1` sets `op_invocations_per_execute=1` to remove inter-invocation pipelining from the timing. Follows the existing `test/custom_ops/` pattern (e.g. `test_mm`) and is registered via `define_custom_op_test_binary` in `targets.bzl`. ghstack-source-id: 405400496 @exported-using-ghexport Differential Revision: [D112906312](https://our.internmc.facebook.com/intern/diff/D112906312/)
🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21116
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…GEMV Pull Request resolved: #21063 The LLM decode AV coop-GEMV reloads the shared V cache once per query head. In grouped-query attention Hq = G * Hkv query heads share each KV head (Llama G=4, Phi G=3, Qwen G=2), and out[q_h, d] = sum_c attn[c, q_h] * V[c, kv_h, d] reads the SAME V texel for every query head in a group. The per-query-head coop shader gives each of the Hq heads its own workgroup, so V -- the dominant traffic (head_dim-wide per context texel, vs a scalar attn weight) -- is read G times. This adds a GQA-reuse AV variant that assigns ONE workgroup per (d4, kv_h): it loads each V texel once and reuses it across all G query heads in the group, producing G output texels. For this bandwidth-bound kernel that cuts V-cache traffic ~Gx. Implementation: - The variant is a codegen flag (`GQA`) on the existing `sdpa_compute_out_coop.glsl` template, not a separate file: one shared header plus two `#ifdef GQA` `main()`s (per-head and GQA-reuse), so the shared setup lives in one place while each algorithm reads end-to-end. It emits the shader `sdpa_compute_out_gqa_coop`. - Reduction reuses the per-head coop shader's shared-memory tree reduction (no subgroup arithmetic), so the variant runs on any Vulkan device -- Adreno and Mali alike -- with no capability gate. - Each thread holds G output accumulators; the array is sized to a compile-time `MAX_GROUP_SIZE` = 8 and the group loop is bounded by the `group_size` = Hq/Hkv spec constant, so the driver fully unrolls it at pipeline creation. - Dispatch (`pick_sdpa_av_shader` + global-wg picker + spec-const wiring in `add_sdpa_compute_out_node`): the GQA variant is selected on the LLM decode coop path when Hq > Hkv, evenly divisible, and G <= 8 (`use_gqa_av_coop`); it sets `group_size` and changes the global workgroup z-dim from Hq to Hkv. Everything else -- MHA (Hq == Hkv), groups exceeding the cap (G > 8, e.g. MQA with Hq > 8), and non-divisible shapes -- falls back to the unchanged per-head `sdpa_compute_out_coop`. (Low-ratio MQA -- Hkv == 1 with Hq <= 8 -- is eligible and takes the GQA path.) - A test-only `gqa_override` knob is threaded through `add_sdpa_compute_out_node` (declared in the new `SDPA.h`): -1 auto-select, 0 force per-head, 1 force GQA, so a benchmark can exercise both AV shaders on the same shape; forcing GQA is VK_CHECK'd against shape eligibility. ghstack-source-id: 405400503 @exported-using-ghexport Differential Revision: [D112906311](https://our.internmc.facebook.com/intern/diff/D112906311/)
…QA AV coop-GEMV Pull Request resolved: #21064 Builds on the GQA-reuse AV coop-GEMV (parent commit). The base `sdpa_compute_out_gqa_coop` shader assigns one head_dim texel (TILE_N4=1) per workgroup x-slot. This adds a head_dim output-tiled variant, `sdpa_compute_out_gqa_coop_tile2` (TILE_N4=2): each workgroup owns 2 head_dim texels and emits G x TILE_N4 outputs, so the per-context-texel attn-weight loads and the shared-memory tree reduction are amortized over twice as many outputs. The AV coop GEMV GLSL is already a TILE_N4-parameterized template (the `partial_n_tile` uniform branch handles the D4 % TILE_N4 != 0 tail), so this change is purely a new codegen variant plus dispatch wiring — no shader-body change. Selection is vendor-adaptive: `pick_sdpa_av_shader` appends the `_tile2` suffix only on Adreno (`graph->device_is_adreno()`). Tiling is a consistent win on Adreno (AV ~1.14-1.63x over the base GQA variant) but a regression on Mali at common decode contexts (~0.67-0.86x, interleaved median-of-N), so Mali and other vendors keep the base `sdpa_compute_out_gqa_coop`. `pick_sdpa_av_global_wg_size` keys off the same `_tile2` suffix: the tiled variant's x-dim collapses from D4 to div_up(D4, 2) since each workgroup now covers 2 head_dim texels. Because the variant is Adreno-only in production, the test-only `gqa_override` knob (see SDPA.h) is extended so tests can pin the variant on any device: `kGqaOverrideForceTile2` / `kGqaOverrideForceBase` force the tiled / base variant regardless of vendor (via `resolve_use_tile2`), giving the tiled shader deterministic coverage on Mali / SwiftShader. `resolve_use_gqa` is unchanged (any non-`ForceNonGqa` value still forces the GQA family, VK_CHECK'd for eligibility). ghstack-source-id: 405400514 @exported-using-ghexport Differential Revision: [D112906313](https://our.internmc.facebook.com/intern/diff/D112906313/)
SS-JIA
approved these changes
Jul 22, 2026
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This PR was created by the merge bot to help merge the original PR into the main branch.
ghstack PR number: #21062 by @SS-JIA
^ Please use this as the source of truth for the PR details, comments, and reviews
ghstack PR base: https://github.com/pytorch/executorch/tree/gh/SS-JIA/575/base
ghstack PR head: https://github.com/pytorch/executorch/tree/gh/SS-JIA/575/head
Merge bot PR base: https://github.com/pytorch/executorch/tree/main
Merge bot PR head: https://github.com/pytorch/executorch/tree/gh/SS-JIA/575/orig
Differential Revision: D112906312
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