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snegi-qtiKomal-Bajaj
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QCLINUX: arm64: dts: qcom: lemans: Add SAIL Mailbox device tree overlay
Add lemans-sail-mb.dtso overlay for Lemans platform providing: - ipcc_computeL1: IPCC Compute-L1 controller - sail_mailbox: SAIL Mailbox device node. Signed-off-by: Sankalp Negi <snegi@qti.qualcomm.com>
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‎arch/arm64/boot/dts/qcom/Makefile‎

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@@ -496,6 +496,7 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-staging.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += lemans-staging.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += lemans-sail-mb.dtbo
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monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo
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‎arch/arm64/boot/dts/qcom/lemans-sail-mb.dtso‎

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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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&soc {
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ipcc_computeL1: qcom,ipcc@488000 {
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compatible = "qcom,ipcc";
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reg = <0x0 0x00488000 0x0 0x1000>;
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interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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num_mbox_chans = <5>;
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};
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sail_mailbox: sail-mailbox@1ffe02c {
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compatible = "qcom,sail-mailbox";
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reg = <0x0 0x01FFE02C 0x0 0x10>,
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<0x0 0x01FFD018 0x0 0x10>,
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<0x0 0x17C0000C 0x0 0x04>;
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mboxes = <&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x2>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL1 0x3>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x4>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x5>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x6>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x7>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL2 0x8>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL1 0x9>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL2 0xa>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL1 0xb>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL0 0xc>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL0 0xd>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL1 0xe>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL2 0xf>,
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<&ipcc_computeL1 IPCC_CLIENT_SAIL3 0x10>;
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memory-region = <&sail_mailbox_mem>,
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<&sail_ota_mem>;
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interrupt-parent = <&ipcc_computeL1>;
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interrupts = <IPCC_CLIENT_SAIL0 0x2 IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL1 0x3 IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL0 0x4 IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL0 0x5 IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL0 0x6 IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL0 0x7 IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL2 0x8 IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL1 0x9 IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL2 0xa IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL1 0xb IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL0 0xc IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL0 0xd IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL1 0xe IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL2 0xf IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_SAIL3 0x10 IRQ_TYPE_EDGE_RISING>;
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sail-handshake-delay = <50000>;
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status = "okay";
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};
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};

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