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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/sound/qcom,shikra-qaif.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Qualcomm Audio Interface on Shikra |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Qualcomm Innovation Center, Inc. <quic_kernel@quicinc.com> |
| 11 | + |
| 12 | +description: |
| 13 | + Qualcomm Audio Interface CPU DAI controller used by the Shikra audio core. |
| 14 | + |
| 15 | +properties: |
| 16 | + compatible: |
| 17 | + const: qcom,shikra-qaif-cpu |
| 18 | + |
| 19 | + reg: |
| 20 | + maxItems: 1 |
| 21 | + |
| 22 | + reg-names: |
| 23 | + const: audio-qaif-core |
| 24 | + |
| 25 | + iommus: |
| 26 | + maxItems: 1 |
| 27 | + |
| 28 | + clocks: |
| 29 | + minItems: 15 |
| 30 | + maxItems: 15 |
| 31 | + |
| 32 | + clock-names: |
| 33 | + items: |
| 34 | + - const: gcc_lpass_config_clk |
| 35 | + - const: gcc_lpass_core_axim_clk |
| 36 | + - const: audio_core_cc_aud_dma_clk |
| 37 | + - const: audio_core_cc_aud_dma_mem_clk |
| 38 | + - const: audio_core_cc_bus_clk |
| 39 | + - const: audio_core_cc_aif_if0_ebit_clk |
| 40 | + - const: audio_core_cc_aif_if0_ibit_clk |
| 41 | + - const: audio_core_cc_aif_if1_ebit_clk |
| 42 | + - const: audio_core_cc_aif_if1_ibit_clk |
| 43 | + - const: audio_core_cc_aif_if2_ebit_clk |
| 44 | + - const: audio_core_cc_aif_if2_ibit_clk |
| 45 | + - const: audio_core_cc_aif_if3_ebit_clk |
| 46 | + - const: audio_core_cc_aif_if3_ibit_clk |
| 47 | + - const: audio_core_cc_ext_mclka_clk |
| 48 | + - const: audio_core_cc_ext_mclkb_clk |
| 49 | + |
| 50 | + interrupts: |
| 51 | + maxItems: 1 |
| 52 | + |
| 53 | + interrupt-names: |
| 54 | + const: qaif-irq-audio-core |
| 55 | + |
| 56 | + '#sound-dai-cells': |
| 57 | + const: 1 |
| 58 | + |
| 59 | + '#address-cells': |
| 60 | + const: 1 |
| 61 | + |
| 62 | + '#size-cells': |
| 63 | + const: 0 |
| 64 | + |
| 65 | + aif-interface: |
| 66 | + $ref: /schemas/types.yaml#/definitions/phandle |
| 67 | + description: TDM/MI2S interface configuration referenced by this controller. |
| 68 | + |
| 69 | +required: |
| 70 | + - compatible |
| 71 | + - reg |
| 72 | + - reg-names |
| 73 | + - iommus |
| 74 | + - clocks |
| 75 | + - clock-names |
| 76 | + - interrupts |
| 77 | + - interrupt-names |
| 78 | + - '#sound-dai-cells' |
| 79 | + |
| 80 | +additionalProperties: false |
| 81 | + |
| 82 | +examples: |
| 83 | + - | |
| 84 | + #include <dt-bindings/clock/qcom,shikra-audiocorecc.h> |
| 85 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 86 | + #include <dt-bindings/interrupt-controller/irq.h> |
| 87 | +
|
| 88 | + audio@a000000 { |
| 89 | + compatible = "qcom,shikra-qaif-cpu"; |
| 90 | + reg = <0x0a000000 0x20000>; |
| 91 | + reg-names = "audio-qaif-core"; |
| 92 | + iommus = <&apps_smmu 0x1c0 0x0>; |
| 93 | + clocks = <&gcc 0>, <&gcc 1>, |
| 94 | + <&audiocorecc AUDIO_CORE_CC_AUD_DMA_CLK>, |
| 95 | + <&audiocorecc AUDIO_CORE_CC_AUD_DMA_MEM_CLK>, |
| 96 | + <&audiocorecc AUDIO_CORE_CC_BUS_CLK>, |
| 97 | + <&audiocorecc AUDIO_CORE_CC_AIF_IF0_EBIT_CLK>, |
| 98 | + <&audiocorecc AUDIO_CORE_CC_AIF_IF0_IBIT_CLK>, |
| 99 | + <&audiocorecc AUDIO_CORE_CC_AIF_IF1_EBIT_CLK>, |
| 100 | + <&audiocorecc AUDIO_CORE_CC_AIF_IF1_IBIT_CLK>, |
| 101 | + <&audiocorecc AUDIO_CORE_CC_AIF_IF2_EBIT_CLK>, |
| 102 | + <&audiocorecc AUDIO_CORE_CC_AIF_IF2_IBIT_CLK>, |
| 103 | + <&audiocorecc AUDIO_CORE_CC_AIF_IF3_EBIT_CLK>, |
| 104 | + <&audiocorecc AUDIO_CORE_CC_AIF_IF3_IBIT_CLK>, |
| 105 | + <&audiocorecc AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK>, |
| 106 | + <&audiocorecc AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK>; |
| 107 | + clock-names = "gcc_lpass_config_clk", "gcc_lpass_core_axim_clk", |
| 108 | + "audio_core_cc_aud_dma_clk", |
| 109 | + "audio_core_cc_aud_dma_mem_clk", |
| 110 | + "audio_core_cc_bus_clk", |
| 111 | + "audio_core_cc_aif_if0_ebit_clk", |
| 112 | + "audio_core_cc_aif_if0_ibit_clk", |
| 113 | + "audio_core_cc_aif_if1_ebit_clk", |
| 114 | + "audio_core_cc_aif_if1_ibit_clk", |
| 115 | + "audio_core_cc_aif_if2_ebit_clk", |
| 116 | + "audio_core_cc_aif_if2_ibit_clk", |
| 117 | + "audio_core_cc_aif_if3_ebit_clk", |
| 118 | + "audio_core_cc_aif_if3_ibit_clk", |
| 119 | + "audio_core_cc_ext_mclka_clk", |
| 120 | + "audio_core_cc_ext_mclkb_clk"; |
| 121 | + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; |
| 122 | + interrupt-names = "qaif-irq-audio-core"; |
| 123 | + #sound-dai-cells = <1>; |
| 124 | + }; |
| 125 | +
|
| 126 | +... |
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