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dt-bindings: sound: qcom: add Shikra QAIF
Document the QAIF CPU DAI controller binding used by Shikra audio. Signed-off-by: Mohammad Rafi Shaik <mohs@qti.qualcomm.com>
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/qcom,shikra-qaif.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Audio Interface on Shikra
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maintainers:
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- Qualcomm Innovation Center, Inc. <quic_kernel@quicinc.com>
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description:
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Qualcomm Audio Interface CPU DAI controller used by the Shikra audio core.
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properties:
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compatible:
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const: qcom,shikra-qaif-cpu
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reg:
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maxItems: 1
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reg-names:
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const: audio-qaif-core
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iommus:
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maxItems: 1
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clocks:
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minItems: 15
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maxItems: 15
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clock-names:
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items:
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- const: gcc_lpass_config_clk
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- const: gcc_lpass_core_axim_clk
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- const: audio_core_cc_aud_dma_clk
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- const: audio_core_cc_aud_dma_mem_clk
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- const: audio_core_cc_bus_clk
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- const: audio_core_cc_aif_if0_ebit_clk
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- const: audio_core_cc_aif_if0_ibit_clk
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- const: audio_core_cc_aif_if1_ebit_clk
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- const: audio_core_cc_aif_if1_ibit_clk
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- const: audio_core_cc_aif_if2_ebit_clk
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- const: audio_core_cc_aif_if2_ibit_clk
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- const: audio_core_cc_aif_if3_ebit_clk
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- const: audio_core_cc_aif_if3_ibit_clk
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- const: audio_core_cc_ext_mclka_clk
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- const: audio_core_cc_ext_mclkb_clk
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interrupts:
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maxItems: 1
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interrupt-names:
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const: qaif-irq-audio-core
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'#sound-dai-cells':
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const: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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aif-interface:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: TDM/MI2S interface configuration referenced by this controller.
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required:
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- compatible
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- reg
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- reg-names
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- iommus
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- '#sound-dai-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,shikra-audiocorecc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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audio@a000000 {
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compatible = "qcom,shikra-qaif-cpu";
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reg = <0x0a000000 0x20000>;
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reg-names = "audio-qaif-core";
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iommus = <&apps_smmu 0x1c0 0x0>;
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clocks = <&gcc 0>, <&gcc 1>,
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<&audiocorecc AUDIO_CORE_CC_AUD_DMA_CLK>,
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<&audiocorecc AUDIO_CORE_CC_AUD_DMA_MEM_CLK>,
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<&audiocorecc AUDIO_CORE_CC_BUS_CLK>,
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<&audiocorecc AUDIO_CORE_CC_AIF_IF0_EBIT_CLK>,
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<&audiocorecc AUDIO_CORE_CC_AIF_IF0_IBIT_CLK>,
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<&audiocorecc AUDIO_CORE_CC_AIF_IF1_EBIT_CLK>,
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<&audiocorecc AUDIO_CORE_CC_AIF_IF1_IBIT_CLK>,
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<&audiocorecc AUDIO_CORE_CC_AIF_IF2_EBIT_CLK>,
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<&audiocorecc AUDIO_CORE_CC_AIF_IF2_IBIT_CLK>,
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<&audiocorecc AUDIO_CORE_CC_AIF_IF3_EBIT_CLK>,
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<&audiocorecc AUDIO_CORE_CC_AIF_IF3_IBIT_CLK>,
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<&audiocorecc AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK>,
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<&audiocorecc AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK>;
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clock-names = "gcc_lpass_config_clk", "gcc_lpass_core_axim_clk",
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"audio_core_cc_aud_dma_clk",
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"audio_core_cc_aud_dma_mem_clk",
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"audio_core_cc_bus_clk",
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"audio_core_cc_aif_if0_ebit_clk",
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"audio_core_cc_aif_if0_ibit_clk",
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"audio_core_cc_aif_if1_ebit_clk",
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"audio_core_cc_aif_if1_ibit_clk",
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"audio_core_cc_aif_if2_ebit_clk",
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"audio_core_cc_aif_if2_ibit_clk",
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"audio_core_cc_aif_if3_ebit_clk",
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"audio_core_cc_aif_if3_ibit_clk",
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"audio_core_cc_ext_mclka_clk",
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"audio_core_cc_ext_mclkb_clk";
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interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "qaif-irq-audio-core";
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#sound-dai-cells = <1>;
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};
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...

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