Skip to content

GLINK wakelock changes (debug) #1247

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
jprakash-qc wants to merge 6 commits into
base: tech/pmic/misc
Choose a base branch
from
Open

GLINK wakelock changes (debug) #1247

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
eee20da
FROMLIST: thermal: qcom: add support for PMIC5 Gen3 ADC thermal monit…
jprakash-qc Feb 9, 2026
0ce7313
FROMLIST: soc: qcom: spmi-pmic: add SUBTYPEs for Glymur/Kaanapali/SM8…
raryan-qcom Apr 20, 2026
7be177d
FROMLIST: arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros
jprakash-qc Apr 30, 2026
3843ab5
FROMLIST: arm64: dts: qcom: lemans-pmics: Add ADC support for PMM8654au
aushasre123 Apr 30, 2026
ee32a8c
FROMLIST: arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU
aushasre123 Apr 30, 2026
8269b21
ucsi wakelock
jprakash-qc May 25, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
93 changes: 93 additions & 0 deletions arch/arm64/boot/dts/qcom/lemans-pmics.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@

#include <dt-bindings/input/input.h>
#include <dt-bindings/spmi/spmi.h>
#include "qcom-adc5-gen3.h"

/ {
thermal-zones {
Expand Down Expand Up @@ -110,6 +111,8 @@
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmm8654au_0_adc ADC5_GEN3_DIE_TEMP(0)>;
io-channel-names = "thermal";
};

pmm8654au_0_pon: pon@1200 {
Expand Down Expand Up @@ -141,6 +144,27 @@
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
};

pmm8654au_0_adc: adc@8000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x8000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;

channel@3 {
reg = <ADC5_GEN3_DIE_TEMP(0)>;
label = "pmm8654au_0_die_temp";
qcom,pre-scaling = <1 1>;
};

channel@8e {
reg = <ADC5_GEN3_VPH_PWR(0)>;
label = "pmm8654au_0_vph_pwr";
qcom,pre-scaling = <1 3>;
};
};

pmm8654au_0_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
Expand Down Expand Up @@ -176,6 +200,29 @@
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmm8654au_1_adc ADC5_GEN3_DIE_TEMP(2)>;
io-channel-names = "thermal";
};

pmm8654au_1_adc: adc@8000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x8000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;

channel@203 {
reg = <ADC5_GEN3_DIE_TEMP(2)>;
label = "pmm8654au_1_die_temp";
qcom,pre-scaling = <1 1>;
};

channel@28e {
reg = <ADC5_GEN3_VPH_PWR(2)>;
label = "pmm8654au_1_vph_pwr";
qcom,pre-scaling = <1 3>;
};
};

pmm8654au_1_gpios: gpio@8800 {
Expand All @@ -200,6 +247,29 @@
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmm8654au_2_adc ADC5_GEN3_DIE_TEMP(4)>;
io-channel-names = "thermal";
};

pmm8654au_2_adc: adc@8000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x8000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x4 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;

channel@403 {
reg = <ADC5_GEN3_DIE_TEMP(4)>;
label = "pmm8654au_2_die_temp";
qcom,pre-scaling = <1 1>;
};

channel@48e {
reg = <ADC5_GEN3_VPH_PWR(4)>;
label = "pmm8654au_2_vph_pwr";
qcom,pre-scaling = <1 3>;
};
};

pmm8654au_2_gpios: gpio@8800 {
Expand All @@ -224,6 +294,29 @@
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmm8654au_3_adc ADC5_GEN3_DIE_TEMP(6)>;
io-channel-names = "thermal";
};

pmm8654au_3_adc: adc@8000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x8000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x6 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;

channel@603 {
reg = <ADC5_GEN3_DIE_TEMP(6)>;
label = "pmm8654au_3_die_temp";
qcom,pre-scaling = <1 1>;
};

channel@68e {
reg = <ADC5_GEN3_VPH_PWR(6)>;
label = "pmm8654au_3_vph_pwr";
qcom,pre-scaling = <1 3>;
};
};

pmm8654au_3_gpios: gpio@8800 {
Expand Down
43 changes: 43 additions & 0 deletions arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@

#include <dt-bindings/input/input.h>
#include <dt-bindings/spmi/spmi.h>
#include "qcom-adc5-gen3.h"

&spmi_bus {
pmm8620au_0: pmic@0 {
Expand All @@ -20,6 +21,27 @@
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
};

pmm8620au_0_adc: adc@8000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x8000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;

channel@3 {
reg = <ADC5_GEN3_DIE_TEMP(0)>;
label = "pmm8620au_0_die_temp";
qcom,pre-scaling = <1 1>;
};

channel@8e {
reg = <ADC5_GEN3_VPH_PWR(0)>;
label = "pmm8620au_0_vph_pwr";
qcom,pre-scaling = <1 3>;
};
};

pmm8620au_0_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
Expand All @@ -37,6 +59,27 @@
#address-cells = <1>;
#size-cells = <0>;

pmm8650au_1_adc: adc@8000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x8000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;

channel@203 {
reg = <ADC5_GEN3_DIE_TEMP(2)>;
label = "pmm8650au_1_die_temp";
qcom,pre-scaling = <1 1>;
};

channel@28e {
reg = <ADC5_GEN3_VPH_PWR(2)>;
label = "pmm8650au_1_vph_pwr";
qcom,pre-scaling = <1 3>;
};
};

pmm8650au_1_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
Expand Down
88 changes: 88 additions & 0 deletions arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,88 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/

#ifndef __DTS_ARM64_QCOM_ADC5_GEN3_H__
#define __DTS_ARM64_QCOM_ADC5_GEN3_H__

/* ADC channels for PMIC5 Gen3 */

#define VIRT_CHAN(sid, chan) ((sid) << 8 | (chan))

#define ADC5_GEN3_REF_GND(sid) VIRT_CHAN(sid, 0x00)
#define ADC5_GEN3_1P25VREF(sid) VIRT_CHAN(sid, 0x01)
#define ADC5_GEN3_VREF_VADC(sid) VIRT_CHAN(sid, 0x02)
#define ADC5_GEN3_DIE_TEMP(sid) VIRT_CHAN(sid, 0x03)

#define ADC5_GEN3_AMUX1_THM(sid) VIRT_CHAN(sid, 0x04)
#define ADC5_GEN3_AMUX2_THM(sid) VIRT_CHAN(sid, 0x05)
#define ADC5_GEN3_AMUX3_THM(sid) VIRT_CHAN(sid, 0x06)
#define ADC5_GEN3_AMUX4_THM(sid) VIRT_CHAN(sid, 0x07)
#define ADC5_GEN3_AMUX5_THM(sid) VIRT_CHAN(sid, 0x08)
#define ADC5_GEN3_AMUX6_THM(sid) VIRT_CHAN(sid, 0x09)
#define ADC5_GEN3_AMUX1_GPIO(sid) VIRT_CHAN(sid, 0x0a)
#define ADC5_GEN3_AMUX2_GPIO(sid) VIRT_CHAN(sid, 0x0b)
#define ADC5_GEN3_AMUX3_GPIO(sid) VIRT_CHAN(sid, 0x0c)
#define ADC5_GEN3_AMUX4_GPIO(sid) VIRT_CHAN(sid, 0x0d)

#define ADC5_GEN3_CHG_TEMP(sid) VIRT_CHAN(sid, 0x10)
#define ADC5_GEN3_USB_SNS_V_16(sid) VIRT_CHAN(sid, 0x11)
#define ADC5_GEN3_VIN_DIV16_MUX(sid) VIRT_CHAN(sid, 0x12)
#define ADC5_GEN3_VREF_BAT_THERM(sid) VIRT_CHAN(sid, 0x15)
#define ADC5_GEN3_IIN_FB(sid) VIRT_CHAN(sid, 0x17)
#define ADC5_GEN3_TEMP_ALARM_LITE(sid) VIRT_CHAN(sid, 0x18)
#define ADC5_GEN3_IIN_SMB(sid) VIRT_CHAN(sid, 0x19)
#define ADC5_GEN3_ICHG_SMB(sid) VIRT_CHAN(sid, 0x1b)
#define ADC5_GEN3_ICHG_FB(sid) VIRT_CHAN(sid, 0xa1)

/* 30k pull-up */
#define ADC5_GEN3_AMUX1_THM_30K_PU(sid) VIRT_CHAN(sid, 0x24)
#define ADC5_GEN3_AMUX2_THM_30K_PU(sid) VIRT_CHAN(sid, 0x25)
#define ADC5_GEN3_AMUX3_THM_30K_PU(sid) VIRT_CHAN(sid, 0x26)
#define ADC5_GEN3_AMUX4_THM_30K_PU(sid) VIRT_CHAN(sid, 0x27)
#define ADC5_GEN3_AMUX5_THM_30K_PU(sid) VIRT_CHAN(sid, 0x28)
#define ADC5_GEN3_AMUX6_THM_30K_PU(sid) VIRT_CHAN(sid, 0x29)
#define ADC5_GEN3_AMUX1_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2a)
#define ADC5_GEN3_AMUX2_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2b)
#define ADC5_GEN3_AMUX3_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2c)
#define ADC5_GEN3_AMUX4_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2d)

/* 100k pull-up */
#define ADC5_GEN3_AMUX1_THM_100K_PU(sid) VIRT_CHAN(sid, 0x44)
#define ADC5_GEN3_AMUX2_THM_100K_PU(sid) VIRT_CHAN(sid, 0x45)
#define ADC5_GEN3_AMUX3_THM_100K_PU(sid) VIRT_CHAN(sid, 0x46)
#define ADC5_GEN3_AMUX4_THM_100K_PU(sid) VIRT_CHAN(sid, 0x47)
#define ADC5_GEN3_AMUX5_THM_100K_PU(sid) VIRT_CHAN(sid, 0x48)
#define ADC5_GEN3_AMUX6_THM_100K_PU(sid) VIRT_CHAN(sid, 0x49)
#define ADC5_GEN3_AMUX1_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4a)
#define ADC5_GEN3_AMUX2_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4b)
#define ADC5_GEN3_AMUX3_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4c)
#define ADC5_GEN3_AMUX4_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4d)

/* 400k pull-up */
#define ADC5_GEN3_AMUX1_THM_400K_PU(sid) VIRT_CHAN(sid, 0x64)
#define ADC5_GEN3_AMUX2_THM_400K_PU(sid) VIRT_CHAN(sid, 0x65)
#define ADC5_GEN3_AMUX3_THM_400K_PU(sid) VIRT_CHAN(sid, 0x66)
#define ADC5_GEN3_AMUX4_THM_400K_PU(sid) VIRT_CHAN(sid, 0x67)
#define ADC5_GEN3_AMUX5_THM_400K_PU(sid) VIRT_CHAN(sid, 0x68)
#define ADC5_GEN3_AMUX6_THM_400K_PU(sid) VIRT_CHAN(sid, 0x69)
#define ADC5_GEN3_AMUX1_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6a)
#define ADC5_GEN3_AMUX2_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6b)
#define ADC5_GEN3_AMUX3_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6c)
#define ADC5_GEN3_AMUX4_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6d)

/* 1/3 Divider */
#define ADC5_GEN3_AMUX1_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8a)
#define ADC5_GEN3_AMUX2_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8b)
#define ADC5_GEN3_AMUX3_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8c)
#define ADC5_GEN3_AMUX4_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8d)

#define ADC5_GEN3_VPH_PWR(sid) VIRT_CHAN(sid, 0x8e)
#define ADC5_GEN3_VBAT_SNS_QBG(sid) VIRT_CHAN(sid, 0x8f)

#define ADC5_GEN3_VBAT_SNS_CHGR(sid) VIRT_CHAN(sid, 0x94)
#define ADC5_GEN3_VBAT_2S_MID_QBG(sid) VIRT_CHAN(sid, 0x96)
#define ADC5_GEN3_VBAT_2S_MID_CHGR(sid) VIRT_CHAN(sid, 0x9d)

#endif /* __DTS_ARM64_QCOM_ADC5_GEN3_H__ */
8 changes: 8 additions & 0 deletions drivers/soc/qcom/socinfo.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -188,7 +188,15 @@ static const char *const pmic_models[] = {
[80] = "PM7550",
[82] = "PMC8380",
[83] = "SMB2360",
[86] = "PM8750B",
[87] = "PMD8028",
[91] = "PMIV0108",
[92] = "PMK8850",
[93] = "PMH0101",
[95] = "SMB2370",
[96] = "PMH0104",
[97] = "PMH0110",
[98] = "PMCX0102",
};

struct socinfo_params {
Expand Down
9 changes: 9 additions & 0 deletions drivers/thermal/qcom/Kconfig
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,15 @@ config QCOM_SPMI_ADC_TM5
Thermal client sets threshold temperature for both warm and cool and
gets updated when a threshold is reached.

config QCOM_SPMI_ADC_TM5_GEN3
tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5 Gen3"
depends on QCOM_SPMI_ADC5_GEN3
help
This enables the auxiliary thermal driver for the ADC5 Gen3 thermal
monitoring device. It shows up as a thermal zone with multiple trip points.
Thermal client sets threshold temperature for both warm and cool and
gets updated when a threshold is reached.

config QCOM_SPMI_TEMP_ALARM
tristate "Qualcomm SPMI PMIC Temperature Alarm"
depends on OF && SPMI && IIO
Expand Down
1 change: 1 addition & 0 deletions drivers/thermal/qcom/Makefile
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,5 +4,6 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o
qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \
tsens-8960.o
obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o
obj-$(CONFIG_QCOM_SPMI_ADC_TM5_GEN3) += qcom-spmi-adc-tm5-gen3.o
obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o
obj-$(CONFIG_QCOM_LMH) += lmh.o
Loading