Align with upstream post of Shikra devicetree changes#1293
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Komal-Bajaj merged 10 commits intoJun 3, 2026
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Arm heterogeneous configurations should have separate PMU nodes for each CPU arch as the arch specific events can be different. The "arm,armv8-pmuv3" compatible is also intended for s/w models rather than specific arch implementations. All the kryo CPUs are missing PMU compatibles, so they can't be fixed. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
…itions The ARM PMUs share the same per-cpu (PPI) interrupt, so we need to switch to interrupt-cells = <4> in the GIC node to allow adding an interrupt partition map phandle as the 4th cell value for GIC_PPI interrupts. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add cache-size properties to the L2 cache for cpu3 (256 KiB) and the shared L3 cache (512 KiB) to allow the kernel to correctly report cache topology. Also correct the dynamic-power-coefficient for cpu3 from 486 to 489 to reflect the accurate power model for that CPU cluster. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
The SCM node requires the CE1 clock to be enabled for cryptographic operations. Add the core clock reference and clock-names property to allow the SCM driver to manage it correctly. Also add #reset-cells = <1> to expose the SCM reset controller interface. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
The reserved-memory list allocates memory regions well below memory node address, such as hyp@80000000 and smem@86000000. Correct the memory node base address from 0xa0000000 to 0x80000000, which is the actual start of DRAM on shikra. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Remove the per-node labels (e.g. cpu0_opp_768mhz, cpu3_opp_1017mhz) from all OPP entries in cpu0_opp_table and cpu3_opp_table. These labels are not referenced anywhere. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Correct the LLCC system cache controller interrupt from SPI 571 to SPI 539, which is the correct GIC SPI line for the LLCC on shikra. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Correct the qfprom efuse node base address from 0x01b40000 to 0x01b44000 and expand the region size from 0x700 to 0x3000. Update the child fuse offsets accordingly: - hstx-trim: node address and reg corrected to 0x25b - gpu-speed-bin: node address and reg corrected from 0x6006 to 0x2006 Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Switch the sdhc_1 interconnect path tags from QCOM_ICC_TAG_ALWAYS and QCOM_ICC_TAG_ACTIVE_ONLY to the RPM-specific RPM_ALWAYS_TAG and RPM_ACTIVE_TAG macros, which are the correct tags for RPM-managed interconnects on this platform. Also correct the power domain reference from RPMHPD_CX to RPMPD_VDDCX to match the RPM power domain provider used on shikra. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
…om remoteprocs Remove the incorrect second interconnect path using MASTER_CRYPTO_CORE0 from both remoteproc_mpss and remoteproc_cdsp nodes. Each remoteproc should only have the single MASTER_AMPSS_M0 to SLAVE_EBI_CH0 path for CPU-to-DDR bandwidth voting. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
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