From 0e0d9a147996559c46f8803cea0f3cc86c683ce5 Mon Sep 17 00:00:00 2001
From: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Date: Mon, 1 Jun 2026 18:37:31 +0530
Subject: [PATCH 01/10] arm64: dts: qcom: shikra: Split PMU nodes for
 heterogeneous CPUs

Arm heterogeneous configurations should have separate PMU nodes
for each CPU arch as the arch specific events can be different.
The "arm,armv8-pmuv3" compatible is also intended for s/w models
rather than specific arch implementations.

All the kryo CPUs are missing PMU compatibles, so they can't
be fixed.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index b9e63c154e279..499c66108c90d 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -276,9 +276,14 @@
 		};
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
-		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+	};
+
+	pmu-a78c {
+		compatible = "arm,cortex-a78-pmu";
+		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
 	};
 
 	psci: psci {
@@ -2141,6 +2146,16 @@
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;
+
+			ppi-partitions {
+				ppi_cluster0: interrupt-partition-0 {
+					affinity = <&cpu0 &cpu1 &cpu2>;
+				};
+
+				ppi_cluster1: interrupt-partition-1 {
+					affinity = <&cpu3>;
+				};
+			};
 		};
 
 		apcs_glb: mailbox@f400000 {

From 9bfa7adb41766bea0d037a633b640459027c28f0 Mon Sep 17 00:00:00 2001
From: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Date: Mon, 1 Jun 2026 18:43:47 +0530
Subject: [PATCH 02/10] arm64: dts: qcom: shikra: switch to interrupt-cells 4
 to add PPI partitions

The ARM PMUs share the same per-cpu (PPI) interrupt, so we need to switch
to interrupt-cells = <4> in the GIC node to allow adding an interrupt
partition map phandle as the 4th cell value for GIC_PPI interrupts.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 368 +++++++++++++--------------
 1 file changed, 184 insertions(+), 184 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 499c66108c90d..8057fce51eee5 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -296,7 +296,7 @@
 
 		glink-edge {
 			compatible = "qcom,glink-rpm";
-			interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+			interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING 0>;
 			qcom,rpm-msg-ram = <&rpm_msg_ram>;
 			mboxes = <&apcs_glb 0>;
 
@@ -358,7 +358,7 @@
 		mpm: interrupt-controller {
 			compatible = "qcom,mpm";
 			qcom,rpm-msg-ram = <&apss_mpm>;
-			interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+			interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING 0>;
 			mboxes = <&apcs_glb 1>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
@@ -464,7 +464,7 @@
 		compatible = "qcom,smp2p";
 		qcom,smem = <94>, <432>;
 
-		interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
+		interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING 0>;
 
 		mboxes = <&apcs_glb 6>;
 
@@ -487,7 +487,7 @@
 		compatible = "qcom,smp2p";
 		qcom,smem = <617>, <616>;
 
-		interrupts = <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>;
+		interrupts = <GIC_SPI 287 IRQ_TYPE_EDGE_RISING 0>;
 
 		mboxes = <&apcs_glb 10>;
 
@@ -510,7 +510,7 @@
 		compatible = "qcom,smp2p";
 		qcom,smem = <435>, <428>;
 
-		interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING 0>;
 
 		mboxes = <&apcs_glb 14>;
 
@@ -544,7 +544,7 @@
 
 		modem_smsm: modem@1 {
 			reg = <1>;
-			interrupts = <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_EDGE_RISING 0>;
 
 			interrupt-controller;
 			#interrupt-cells = <2>;
@@ -574,7 +574,7 @@
 			compatible = "qcom,shikra-tlmm";
 			reg = <0x0 0x00500000 0x0 0x700000>;
 
-			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -1008,7 +1008,7 @@
 			compatible = "qcom,shikra-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
 			reg = <0x0 0x00c91000 0x0 0x1000>;
 
-			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>;
 
 			interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
 					 &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>;
@@ -1058,7 +1058,7 @@
 			      <0x0 0x0f00000 0x0 0x80000>,
 			      <0x0 0x1000000 0x0 0x80000>;
 			reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
-			interrupts = <GIC_SPI 571 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 571 IRQ_TYPE_LEVEL_HIGH 0>;
 		};
 
 		gcc: clock-controller@1400000 {
@@ -1185,7 +1185,7 @@
 		cryptobam: dma-controller@1b04000 {
 			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
 			reg = <0x0 0x01b04000 0x0 0x24000>;
-			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>;
 			#dma-cells = <1>;
 			iommus = <&apps_smmu 0x84 0x0011>,
 				 <&apps_smmu 0x86 0x0011>,
@@ -1260,8 +1260,8 @@
 			compatible = "qcom,shikra-tsens", "qcom,tsens-v2";
 			reg = <0x0 0x04411000 0x0 0x1000>,
 			      <0x0 0x04410000 0x0 0x1000>;
-			interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
 			interrupt-names = "uplow",
 					  "critical";
 			#qcom,sensors = <14>;
@@ -1301,8 +1301,8 @@
 
 			iommus = <&apps_smmu 0xc0 0x0>;
 
-			interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH 0>;
 			interrupt-names = "hc_irq",
 					  "pwr_irq";
 
@@ -1361,8 +1361,8 @@
 			compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x0 0x4784000 0x0 0x1000>;
 
-			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
 			interrupt-names = "hc_irq", "pwr_irq";
 
 			bus-width = <4>;
@@ -1422,10 +1422,10 @@
 					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
 			assigned-clock-rates = <19200000>, <133333333>;
 
-			interrupts-extended = <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
-					      <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
-					      <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
-					      <&intc GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
+					      <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>,
+					      <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
+					      <&intc GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>;
 			interrupt-names = "dwc_usb3",
 					  "pwr_event",
 					  "qusb2_phy",
@@ -1483,7 +1483,7 @@
 				    "cx_mem",
 				    "cx_dbgc";
 
-			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>;
 
 			clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
 				 <&gpucc GPU_CC_AHB_CLK>,
@@ -1590,15 +1590,15 @@
 			#iommu-cells = <2>;
 			#global-interrupts = <1>;
 
-			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;
 
 			clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>,
 				<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
@@ -1615,7 +1615,7 @@
 		iris: video-codec@5a00000 {
 			compatible = "qcom,shikra-iris", "qcom,qcm2290-venus";
 			reg = <0 0x5a00000 0 0x200000>;
-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
 
 			power-domains = <&gcc GCC_VENUS_GDSC>,
 					<&gcc GCC_VCODEC0_GDSC>,
@@ -1726,14 +1726,14 @@
 				      "vfe1",
 				      "vfe1_cphy_rx";
 
-			interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
-				     <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
-				     <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
-				     <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
-				     <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
-				     <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
-				     <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
-				     <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+			interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 212 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 72 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 73 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 309 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 310 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 211 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 213 IRQ_TYPE_EDGE_RISING 0>;
 			interrupt-names = "csid0",
 					  "csid1",
 					  "csiphy0",
@@ -1777,7 +1777,7 @@
 			compatible = "qcom,shikra-cci", "qcom,msm8996-cci";
 
 			reg = <0x0 0x05c1b000 0x0 0x1000>;
-			interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
+			interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING 0>;
 			power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
 			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
 				 <&gcc GCC_CAMSS_CCI_0_CLK>;
@@ -1812,7 +1812,7 @@
 			compatible = "qcom,shikra-mdss";
 			reg = <0x0 0x05e00000 0x0 0x1000>;
 			reg-names = "mdss";
-			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
 
@@ -2040,71 +2040,71 @@
 			#iommu-cells = <2>;
 			#global-interrupts = <1>;
 
-			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
 		};
 
 		wifi: wifi@c800000 {
@@ -2112,18 +2112,18 @@
 			reg = <0x0 0x0c800000 0x0 0x800000>;
 			reg-names = "membase";
 			memory-region = <&wlan_mem>;
-			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>;
 			iommus = <&apps_smmu 0x1a0 0x1>;
 			qcom,msa-fixed-perm;
 
@@ -2135,9 +2135,9 @@
 			reg = <0x0 0xf200000 0x0 0x10000>, /* GICD */
 			      <0x0 0xf240000 0x0 0x80000>; /* GICR * 4 regions */
 
-			interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 
-			#interrupt-cells = <3>;
+			#interrupt-cells = <4>;
 			interrupt-controller;
 
 			#redistributor-regions = <1>;
@@ -2167,8 +2167,8 @@
 		watchdog@f410000 {
 			compatible = "qcom,apss-wdt-shikra", "qcom,kpss-wdt";
 			reg = <0x0 0x0f410000 0x0 0x1000>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&sleep_clk>;
 		};
 
@@ -2184,49 +2184,49 @@
 				reg = <0x0f421000 0x1000>,
 				      <0x0f422000 0x1000>;
 				frame-number = <0>;
-				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 			};
 
 			frame@f423000 {
 				reg = <0x0f423000 0x1000>;
 				frame-number = <1>;
-				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 				status = "disabled";
 			};
 
 			frame@f425000 {
 				reg = <0x0f425000 0x1000>;
 				frame-number = <2>;
-				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
 				status = "disabled";
 			};
 
 			frame@f427000 {
 				reg = <0x0f427000 0x1000>;
 				frame-number = <3>;
-				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 				status = "disabled";
 			};
 
 			frame@f429000 {
 				reg = <0x0f429000 0x1000>;
 				frame-number = <4>;
-				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 				status = "disabled";
 			};
 
 			frame@f42b000 {
 				reg = <0x0f42b000 0x1000>;
 				frame-number = <5>;
-				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>;
 				status = "disabled";
 			};
 
 			frame@f42d000 {
 				reg = <0x0f42d000 0x1000>;
 				frame-number = <6>;
-				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
 				status = "disabled";
 			};
 		};
@@ -2235,22 +2235,22 @@
 			compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma";
 			reg = <0x0 0x04a00000 0x0 0x60000>;
 
-			interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH 0>;
 
 			dma-channels = <16>;
 			dma-channel-mask = <0xff>;
@@ -2291,7 +2291,7 @@
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x4a80000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 				clock-names = "se";
@@ -2323,7 +2323,7 @@
 				compatible = "qcom,geni-spi";
 				reg = <0x0 0x4a80000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 				clock-names = "se";
@@ -2352,7 +2352,7 @@
 				compatible = "qcom,geni-debug-uart";
 				reg = <0x0 0x04a80000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 				clock-names = "se";
@@ -2374,7 +2374,7 @@
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x4a84000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 				clock-names = "se";
@@ -2406,7 +2406,7 @@
 				compatible = "qcom,geni-uart";
 				reg = <0x0 0x04a84000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 				clock-names = "se";
@@ -2428,7 +2428,7 @@
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x4a88000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 				clock-names = "se";
@@ -2460,7 +2460,7 @@
 				compatible = "qcom,geni-spi";
 				reg = <0x0 0x4a88000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 				clock-names = "se";
@@ -2489,7 +2489,7 @@
 				compatible = "qcom,geni-uart";
 				reg = <0x0 0x04a88000 0x0 0x4000>;
 
-				interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+				interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>,
 						      <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
@@ -2512,7 +2512,7 @@
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x4a8c000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 				clock-names = "se";
@@ -2544,7 +2544,7 @@
 				compatible = "qcom,geni-uart";
 				reg = <0x0 0x04a8c000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 				clock-names = "se";
@@ -2566,7 +2566,7 @@
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x4a90000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 				clock-names = "se";
@@ -2598,7 +2598,7 @@
 				compatible = "qcom,geni-uart";
 				reg = <0x0 0x04a90000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 				clock-names = "se";
@@ -2620,7 +2620,7 @@
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x4a94000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 				clock-names = "se";
@@ -2652,7 +2652,7 @@
 				compatible = "qcom,geni-spi";
 				reg = <0x0 0x4a94000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 				clock-names = "se";
@@ -2681,7 +2681,7 @@
 				compatible = "qcom,geni-uart";
 				reg = <0x0 0x04a94000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 				clock-names = "se";
@@ -2703,7 +2703,7 @@
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x4a98000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 				clock-names = "se";
@@ -2735,7 +2735,7 @@
 				compatible = "qcom,geni-spi";
 				reg = <0x0 0x4a98000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 				clock-names = "se";
@@ -2764,7 +2764,7 @@
 				compatible = "qcom,geni-uart";
 				reg = <0x0 0x04a98000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 				clock-names = "se";
@@ -2786,7 +2786,7 @@
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x4a9c000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 				clock-names = "se";
@@ -2818,7 +2818,7 @@
 				compatible = "qcom,geni-uart";
 				reg = <0x0 0x04a9c000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 				clock-names = "se";
@@ -2840,7 +2840,7 @@
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x4aa0000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
 				clock-names = "se";
@@ -2872,7 +2872,7 @@
 				compatible = "qcom,geni-spi";
 				reg = <0x0 0x4aa0000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
 				clock-names = "se";
@@ -2901,7 +2901,7 @@
 				compatible = "qcom,geni-uart";
 				reg = <0x0 0x04aa0000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
 				clock-names = "se";
@@ -2923,7 +2923,7 @@
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x4aa4000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>;
 				clock-names = "se";
@@ -2955,7 +2955,7 @@
 				compatible = "qcom,geni-uart";
 				reg = <0x0 0x04aa4000 0x0 0x4000>;
 
-				interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
 
 				clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>;
 				clock-names = "se";
@@ -2977,7 +2977,7 @@
 		bam_dmux_dma: dma-controller@6044000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x0 0x06044000 0x0 0x19000>;
-			interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING 0>;
 			#dma-cells = <1>;
 			qcom,ee = <0>;
 
@@ -2990,7 +2990,7 @@
 			compatible = "qcom,shikra-mpss-pas";
 			reg = <0x0 0x06080000 0x0 0x100>;
 
-			interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
+			interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING 0>,
 					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 					      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -3021,7 +3021,7 @@
 			status = "disabled";
 
 			glink-edge {
-				interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
+				interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING 0>;
 				mboxes = <&apcs_glb 12>;
 				qcom,remote-pid = <1>;
 				label = "mpss";
@@ -4287,7 +4287,7 @@
 			compatible = "qcom,shikra-cdsp-pas";
 			reg = <0x0 0x0b300000 0x0 0x100000>;
 
-			interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
+			interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING 0>,
 					      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 					      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 					      <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -4318,7 +4318,7 @@
 			status = "disabled";
 
 			glink-edge {
-				interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;
+				interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING 0>;
 				mboxes = <&apcs_glb 4>;
 				qcom,remote-pid = <5>;
 				label = "cdsp";
@@ -4379,7 +4379,7 @@
 			compatible = "qcom,shikra-lpaicp-pas";
 			reg = <0x0 0x0b800000 0x0 0x200000>;
 
-			interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
+			interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING 0>,
 					      <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>,
 					      <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>,
 					      <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>,
@@ -4402,7 +4402,7 @@
 			status = "disabled";
 
 			glink-edge {
-				interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
+				interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING 0>;
 				mboxes = <&apcs_glb 9>;
 				qcom,remote-pid = <26>;
 				label = "lpaicp";
@@ -4427,8 +4427,8 @@
 			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
 			clock-names = "xo", "alternate";
 
-			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
 			interrupt-names = "dcvsh-irq-0",
 					  "dcvsh-irq-1";
 
@@ -4723,9 +4723,9 @@
 	timer {
 		compatible = "arm,armv8-timer";
 
-		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
+		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW 0>,
+			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>,
+			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW 0>,
+			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW 0>;
 	};
 };

From aa35e578c448a2a233ff959146e4ee70599c1d25 Mon Sep 17 00:00:00 2001
From: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Date: Tue, 2 Jun 2026 14:30:35 +0530
Subject: [PATCH 03/10] arm64: dts: qcom: shikra: add cache sizes and fix cpu3
 power coefficient

Add cache-size properties to the L2 cache for cpu3 (256 KiB) and the
shared L3 cache (512 KiB) to allow the kernel to correctly report cache
topology.

Also correct the dynamic-power-coefficient for cpu3 from 486 to 489 to
reflect the accurate power model for that CPU cluster.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 8057fce51eee5..3f2d249e19c3b 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -120,7 +120,7 @@
 			enable-method = "psci";
 			next-level-cache = <&l2_3>;
 			capacity-dmips-mhz = <1946>;
-			dynamic-power-coefficient = <486>;
+			dynamic-power-coefficient = <489>;
 			clocks = <&cpufreq_hw 1>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			#cooling-cells = <2>;
@@ -135,6 +135,7 @@
 				cache-level = <2>;
 				cache-unified;
 				next-level-cache = <&l3>;
+				cache-size = <0x40000>;
 			};
 		};
 
@@ -164,6 +165,7 @@
 			compatible = "cache";
 			cache-level = <3>;
 			cache-unified;
+			cache-size = <0x80000>;
 		};
 	};
 

From 075193dc751177b87f6b11f8eef2e9a6a240e70e Mon Sep 17 00:00:00 2001
From: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Date: Tue, 2 Jun 2026 14:34:56 +0530
Subject: [PATCH 04/10] arm64: dts: qcom: shikra: add SCM clock and reset-cells
 to firmware node

The SCM node requires the CE1 clock to be enabled for cryptographic
operations. Add the core clock reference and clock-names property to
allow the SCM driver to manage it correctly.

Also add #reset-cells = <1> to expose the SCM reset controller
interface.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 3f2d249e19c3b..502cd2cdc50e6 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -186,7 +186,10 @@
 	firmware {
 		scm {
 			compatible = "qcom,scm-shikra", "qcom,scm";
+			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
+			clock-names = "core";
 			qcom,dload-mode = <&tcsr_regs 0x13000>;
+			#reset-cells = <1>;
 			interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
 					 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
 		};

From 0853197b50181ab591216859e3a7545dcef6d5cf Mon Sep 17 00:00:00 2001
From: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Date: Tue, 2 Jun 2026 14:36:13 +0530
Subject: [PATCH 05/10] arm64: dts: qcom: shikra: fix memory node base address

The reserved-memory list allocates memory regions well below memory
node address, such as hyp@80000000 and smem@86000000.
Correct the memory node base address from 0xa0000000 to 0x80000000,
which is the actual start of DRAM on shikra.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 502cd2cdc50e6..5ab2f0d628cc8 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -195,10 +195,10 @@
 		};
 	};
 
-	memory@a0000000 {
+	memory@80000000 {
 		device_type = "memory";
 		/* We expect the bootloader to fill in the size */
-		reg = <0x0 0xa0000000 0x0 0x0>;
+		reg = <0x0 0x80000000 0x0 0x0>;
 	};
 
 	modem-etm0 {

From 83f7248bcf156f72516542a4d0ec48c5cb61de43 Mon Sep 17 00:00:00 2001
From: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Date: Tue, 2 Jun 2026 14:40:10 +0530
Subject: [PATCH 06/10] arm64: dts: qcom: shikra: drop unused labels from OPP
 table entries

Remove the per-node labels (e.g. cpu0_opp_768mhz, cpu3_opp_1017mhz)
from all OPP entries in cpu0_opp_table and cpu3_opp_table. These labels
are not referenced anywhere.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 5ab2f0d628cc8..8ca85d6447b28 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -220,32 +220,32 @@
 		compatible = "operating-points-v2";
 		opp-shared;
 
-		cpu0_opp_768mhz: opp-768000000 {
+		opp-768000000 {
 			opp-hz = /bits/ 64 <768000000>;
 			opp-peak-kBps = <1200000 17817600>;
 		};
 
-		cpu0_opp_1017mhz: opp-1017600000 {
+		opp-1017600000 {
 			opp-hz = /bits/ 64 <1017600000>;
 			opp-peak-kBps = <2188000 25804800>;
 		};
 
-		cpu0_opp_1094mhz: opp-1094400000 {
+		opp-1094400000 {
 			opp-hz = /bits/ 64 <1094400000>;
 			opp-peak-kBps = <3072000 30105600>;
 		};
 
-		cpu0_opp_1497mhz: opp-1497600000 {
+		opp-1497600000 {
 			opp-hz = /bits/ 64 <1497600000>;
 			opp-peak-kBps = <4068000 38707200>;
 		};
 
-		cpu0_opp_1612mhz: opp-1612800000 {
+		opp-1612800000 {
 			opp-hz = /bits/ 64 <1612800000>;
 			opp-peak-kBps = <6220000 43008000>;
 		};
 
-		cpu0_opp_1804mhz: opp-1804800000 {
+		opp-1804800000 {
 			opp-hz = /bits/ 64 <1804800000>;
 			opp-peak-kBps = <7216000 43622400>;
 		};
@@ -255,27 +255,27 @@
 		compatible = "operating-points-v2";
 		opp-shared;
 
-		cpu3_opp_1017mhz: opp-1017600000 {
+		opp-1017600000 {
 			opp-hz = /bits/ 64 <1017600000>;
 			opp-peak-kBps = <2188000 25804800>;
 		};
 
-		cpu3_opp_1190mhz: opp-1190400000 {
+		opp-1190400000 {
 			opp-hz = /bits/ 64 <1190400000>;
 			opp-peak-kBps = <3072000 30105600>;
 		};
 
-		cpu3_opp_1497mhz: opp-1497600000 {
+		opp-1497600000 {
 			opp-hz = /bits/ 64 <1497600000>;
 			opp-peak-kBps = <4068000 38707200>;
 		};
 
-		cpu3_opp_1708mhz: opp-1708800000 {
+		opp-1708800000 {
 			opp-hz = /bits/ 64 <1708800000>;
 			opp-peak-kBps = <6220000 43008000>;
 		};
 
-		cpu3_opp_1900mhz: opp-1900800000 {
+		opp-1900800000 {
 			opp-hz = /bits/ 64 <1900800000>;
 			opp-peak-kBps = <7216000 43622400>;
 		};

From 7912c195de53cedb51373b043b8358de3dcec0aa Mon Sep 17 00:00:00 2001
From: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Date: Tue, 2 Jun 2026 14:44:28 +0530
Subject: [PATCH 07/10] arm64: dts: qcom: shikra: fix LLCC interrupt number

Correct the LLCC system cache controller interrupt from SPI 571 to
SPI 539, which is the correct GIC SPI line for the LLCC on shikra.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 8ca85d6447b28..55a9b3aab4b62 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -1062,8 +1062,10 @@
 			reg = <0x0 0x00e00000 0x0 0x80000>,
 			      <0x0 0x0f00000 0x0 0x80000>,
 			      <0x0 0x1000000 0x0 0x80000>;
-			reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
-			interrupts = <GIC_SPI 571 IRQ_TYPE_LEVEL_HIGH 0>;
+			reg-names = "llcc0_base",
+				    "llcc1_base",
+				    "llcc_broadcast_base";
+			interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH 0>;
 		};
 
 		gcc: clock-controller@1400000 {

From 0ca9398b285c57519747a45926c8ea8d969466e9 Mon Sep 17 00:00:00 2001
From: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Date: Tue, 2 Jun 2026 14:53:18 +0530
Subject: [PATCH 08/10] arm64: dts: qcom: shikra: fix qfprom base address and
 child offsets

Correct the qfprom efuse node base address from 0x01b40000 to
0x01b44000 and expand the region size from 0x700 to 0x3000.

Update the child fuse offsets accordingly:
- hstx-trim: node address and reg corrected to 0x25b
- gpu-speed-bin: node address and reg corrected from 0x6006 to 0x2006

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 55a9b3aab4b62..bd1798e5eff68 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -1224,19 +1224,19 @@
 			interconnect-names = "memory";
 		};
 
-		qfprom: efuse@1b40000 {
+		qfprom: efuse@1b44000 {
 			compatible = "qcom,shikra-qfprom", "qcom,qfprom";
-			reg = <0x0 0x01b40000 0x0 0x700>;
+			reg = <0x0 0x01b44000 0x0 0x3000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			qusb2_hstx_trim_1: hstx-trim@258 {
+			qusb2_hstx_trim_1: hstx-trim@25b {
 				reg = <0x25b 0x1>;
 				bits = <1 4>;
 			};
 
-			gpu_speed_bin: gpu-speed-bin@6006 {
-				reg = <0x6006 0x2>;
+			gpu_speed_bin: gpu-speed-bin@2006 {
+				reg = <0x2006 0x2>;
 				bits = <5 8>;
 			};
 		};

From 897a8f06f6bf87cfa40e4c2af9346ca6c9bde9b3 Mon Sep 17 00:00:00 2001
From: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Date: Tue, 2 Jun 2026 14:55:53 +0530
Subject: [PATCH 09/10] arm64: dts: qcom: shikra: fix sdhc_1 interconnect tags
 and power domain

Switch the sdhc_1 interconnect path tags from QCOM_ICC_TAG_ALWAYS and
QCOM_ICC_TAG_ACTIVE_ONLY to the RPM-specific RPM_ALWAYS_TAG and
RPM_ACTIVE_TAG macros, which are the correct tags for RPM-managed
interconnects on this platform.

Also correct the power domain reference from RPMHPD_CX to RPMPD_VDDCX
to match the RPM power domain provider used on shikra.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index bd1798e5eff68..f954cb20b020f 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -1320,14 +1320,14 @@
 				      "core",
 				      "xo";
 
-			interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
-					&mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
-					<&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
-					&config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG
+					&mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+					<&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+					&config_noc SLAVE_SDCC_1 RPM_ACTIVE_TAG>;
 			interconnect-names = "sdhc-ddr",
 					     "cpu-sdhc";
 
-			power-domains = <&rpmpd RPMHPD_CX>;
+			power-domains = <&rpmpd RPMPD_VDDCX>;
 			operating-points-v2 = <&sdhc1_opp_table>;
 
 			qcom,dll-config = <0x000f642c>;

From 3cd2d7a43eeccfeef194fbd93535e27ea64be38a Mon Sep 17 00:00:00 2001
From: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Date: Tue, 2 Jun 2026 14:59:17 +0530
Subject: [PATCH 10/10] arm64: dts: qcom: shikra: remove spurious crypto
 interconnect path from remoteprocs

Remove the incorrect second interconnect path using MASTER_CRYPTO_CORE0
from both remoteproc_mpss and remoteproc_cdsp nodes.

Each remoteproc should only have the single MASTER_AMPSS_M0 to
SLAVE_EBI_CH0 path for CPU-to-DDR bandwidth voting.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index f954cb20b020f..e7f6e0be85172 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -3014,8 +3014,6 @@
 			clock-names = "xo";
 
 			interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
-					 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
-					<&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
 					 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
 
 			power-domains = <&rpmpd RPMHPD_CX>;
@@ -4311,8 +4309,6 @@
 			clock-names = "xo";
 
 			interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
-					 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
-					<&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
 					 &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
 
 			power-domains = <&rpmpd RPMHPD_CX>;