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Clk gp mnd dt #1297

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Merged
Komal-Bajaj merged 2 commits into from
Jun 4, 2026
Merged

Clk gp mnd dt #1297

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cc3d966
FROMLIST: arm64: dts: qcom: Add gp_mn pin state for GP M/N clock output
taniyadas20 Jun 2, 2026
5ac7101
FROMLIST: arm64: dts: qcom: Add GP M/N clock controller node for SA87…
taniyadas20 Jun 2, 2026
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21 changes: 21 additions & 0 deletions arch/arm64/boot/dts/qcom/kodiak.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -4408,6 +4408,20 @@
};
};

gp_mn: clock-controller@88d3000 {
compatible = "qcom,clk-gp-mnd";
reg = <0x0 0x088d3000 0x0 0xc>;
clocks = <&gcc GCC_PDM_XO4_CLK>,
<&gcc GCC_PDM_AHB_CLK>;
clock-names = "pdm_clk", "ahb_clk";
clock-output-names = "gp_mn_clk";
#clock-cells = <0>;
pinctrl-names = "active";
pinctrl-0 = <&gp_mn_active>;
assigned-clocks = <&gcc GCC_PDM_XO4_CLK>;
assigned-clock-rates = <4800000>;
};

qspi: spi@88dc000 {
compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
reg = <0 0x088dc000 0 0x1000>;
Expand Down Expand Up @@ -5901,6 +5915,13 @@
function = "edp_hot";
};

gp_mn_active: gp_mn_active-state {
pins = "gpio35";
function = "gp_mn";
drive-strength = <2>;
bias-disable;
};

mi2s0_data0: mi2s0-data0-state {
pins = "gpio98";
function = "mi2s0_data0";
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21 changes: 21 additions & 0 deletions arch/arm64/boot/dts/qcom/lemans.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -4003,6 +4003,20 @@
};
};

gp_mn: clock-controller@88d3000 {
compatible = "qcom,clk-gp-mnd";
reg = <0x0 0x088d3000 0x0 0xc>;
clocks = <&gcc GCC_PDM_XO4_CLK>,
<&gcc GCC_PDM_AHB_CLK>;
clock-names = "pdm_clk", "ahb_clk";
clock-output-names = "gp_mn_clk";
#clock-cells = <0>;
pinctrl-names = "active";
pinctrl-0 = <&gp_mn_active>;
assigned-clocks = <&gcc GCC_PDM_XO4_CLK>;
assigned-clock-rates = <4800000>;
};

usb_0_hsphy: phy@88e4000 {
compatible = "qcom,sa8775p-usb-hs-phy",
"qcom,usb-snps-hs-5nm-phy";
Expand Down Expand Up @@ -5692,6 +5706,13 @@
bias-disable;
};

gp_mn_active: gp_mn_active-state {
pins = "gpio35";
function = "gp_mn";
drive-strength = <2>;
bias-disable;
};

hs0_mi2s_active: hs0-mi2s-active-state {
pins = "gpio114", "gpio115", "gpio116", "gpio117";
function = "hs0_mi2s";
Expand Down
21 changes: 21 additions & 0 deletions arch/arm64/boot/dts/qcom/monaco.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -4906,6 +4906,20 @@
};
};

gp_mn: clock-controller@88d3000 {
compatible = "qcom,clk-gp-mnd";
reg = <0x0 0x088d3000 0x0 0xc>;
clocks = <&gcc GCC_PDM_XO4_CLK>,
<&gcc GCC_PDM_AHB_CLK>;
clock-names = "pdm_clk", "ahb_clk";
clock-output-names = "gp_mn_clk";
#clock-cells = <0>;
pinctrl-names = "active";
pinctrl-0 = <&gp_mn_active>;
assigned-clocks = <&gcc GCC_PDM_XO4_CLK>;
assigned-clock-rates = <4800000>;
};

usb_1_hsphy: phy@8904000 {
compatible = "qcom,qcs8300-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
Expand Down Expand Up @@ -6472,6 +6486,13 @@
bias-disable;
};

gp_mn_active: gp_mn_active-state {
pins = "gpio32";
function = "gp_mn";
drive-strength = <2>;
bias-disable;
};

hs0_mi2s_active: hs0-mi2s-active-state {
pins = "gpio106", "gpio107", "gpio108", "gpio109";
function = "hs0_mi2s";
Expand Down