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Merge tag 'v6.18.18' into qcom-6.18.y (#366)
Merge tag 'v6.18.18' into qcom-6.18.y
2 parents 80336b7 + 3544d1e commit 064f705

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Documentation/PCI/endpoint/pci-vntb-howto.rst

Lines changed: 7 additions & 7 deletions
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@@ -52,14 +52,14 @@ pci-epf-vntb device, the following commands can be used::
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# cd /sys/kernel/config/pci_ep/
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# mkdir functions/pci_epf_vntb/func1
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55-
The "mkdir func1" above creates the pci-epf-ntb function device that will
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The "mkdir func1" above creates the pci-epf-vntb function device that will
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be probed by pci_epf_vntb driver.
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The PCI endpoint framework populates the directory with the following
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configurable fields::
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# ls functions/pci_epf_ntb/func1
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baseclass_code deviceid msi_interrupts pci-epf-ntb.0
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# ls functions/pci_epf_vntb/func1
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baseclass_code deviceid msi_interrupts pci-epf-vntb.0
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progif_code secondary subsys_id vendorid
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cache_line_size interrupt_pin msix_interrupts primary
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revid subclass_code subsys_vendor_id
@@ -111,13 +111,13 @@ A sample configuration for virtual NTB driver for virtual PCI bus::
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# echo 0x080A > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vntb_pid
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# echo 0x10 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vbus_number
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Binding pci-epf-ntb Device to EP Controller
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Binding pci-epf-vntb Device to EP Controller
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--------------------------------------------
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NTB function device should be attached to PCI endpoint controllers
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connected to the host.
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# ln -s controllers/5f010000.pcie_ep functions/pci-epf-ntb/func1/primary
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# ln -s controllers/5f010000.pcie_ep functions/pci_epf_vntb/func1/primary
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Once the above step is completed, the PCI endpoint controllers are ready to
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establish a link with the host.
@@ -139,7 +139,7 @@ lspci Output at Host side
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-------------------------
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Note that the devices listed here correspond to the values populated in
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"Creating pci-epf-ntb Device" section above::
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"Creating pci-epf-vntb Device" section above::
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# lspci
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00:00.0 PCI bridge: Freescale Semiconductor Inc Device 0000 (rev 01)
@@ -152,7 +152,7 @@ lspci Output at EP Side / Virtual PCI bus
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-----------------------------------------
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Note that the devices listed here correspond to the values populated in
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"Creating pci-epf-ntb Device" section above::
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"Creating pci-epf-vntb Device" section above::
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# lspci
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10:00.0 Unassigned class [ffff]: Dawicontrol Computersysteme GmbH Device 1234 (rev ff)

Documentation/admin-guide/cgroup-v2.rst

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@@ -2538,10 +2538,10 @@ Cpuset Interface Files
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Users can manually set it to a value that is different from
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"cpuset.cpus". One constraint in setting it is that the list of
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CPUs must be exclusive with respect to "cpuset.cpus.exclusive"
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of its sibling. If "cpuset.cpus.exclusive" of a sibling cgroup
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isn't set, its "cpuset.cpus" value, if set, cannot be a subset
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of it to leave at least one CPU available when the exclusive
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CPUs are taken away.
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and "cpuset.cpus.exclusive.effective" of its siblings. Another
2542+
constraint is that it cannot be a superset of "cpuset.cpus"
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of its sibling in order to leave at least one CPU available to
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that sibling when the exclusive CPUs are taken away.
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25462546
For a parent cgroup, any one of its exclusive CPUs can only
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be distributed to at most one of its child cgroups. Having an

Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml

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@@ -122,11 +122,11 @@ properties:
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vdda-phy-supply:
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description:
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Phandle to a regulator supply to PHY core block.
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Phandle to a 0.88V regulator supply to CSI PHYs.
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127127
vdda-pll-supply:
128128
description:
129-
Phandle to 1.8V regulator supply to PHY refclk pll block.
129+
Phandle to 1.2V regulator supply to CSI PHYs pll block.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports

Documentation/devicetree/bindings/sound/asahi-kasei,ak4458.yaml

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@@ -21,10 +21,10 @@ properties:
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reg:
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maxItems: 1
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24-
avdd-supply:
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AVDD-supply:
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description: Analog power supply
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27-
dvdd-supply:
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DVDD-supply:
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description: Digital power supply
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reset-gpios:
@@ -60,7 +60,7 @@ allOf:
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properties:
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dsd-path: false
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63-
additionalProperties: false
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unevaluatedProperties: false
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examples:
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- |

Documentation/devicetree/bindings/sound/asahi-kasei,ak5558.yaml

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@@ -19,10 +19,10 @@ properties:
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reg:
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maxItems: 1
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22-
avdd-supply:
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AVDD-supply:
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description: A 1.8V supply that powers up the AVDD pin.
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25-
dvdd-supply:
25+
DVDD-supply:
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description: A 1.2V supply that powers up the DVDD pin.
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reset-gpios:

Documentation/driver-api/dpll.rst

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@@ -198,26 +198,28 @@ be requested with the same attribute with ``DPLL_CMD_DEVICE_SET`` command.
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================================== ======================================
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Device may also provide ability to adjust a signal phase on a pin.
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If pin phase adjustment is supported, minimal and maximal values that pin
202-
handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond
203-
with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX``
201+
If pin phase adjustment is supported, minimal and maximal values and
202+
granularity that pin handle shall be provided to the user on
203+
``DPLL_CMD_PIN_GET`` respond with ``DPLL_A_PIN_PHASE_ADJUST_MIN``,
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``DPLL_A_PIN_PHASE_ADJUST_MAX`` and ``DPLL_A_PIN_PHASE_ADJUST_GRAN``
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attributes. Configured phase adjust value is provided with
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``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be
206207
requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.
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208-
=============================== ======================================
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``DPLL_A_PIN_ID`` configured pin id
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``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
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``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
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``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
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adjustment on parent dpll device
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``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting
215-
configuration on given parent dpll
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device
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``DPLL_A_PIN_PARENT_ID`` parent dpll device id
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``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
219-
between a pin and parent dpll device
220-
=============================== ======================================
209+
================================ ==========================================
210+
``DPLL_A_PIN_ID`` configured pin id
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``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attr granularity of phase adjustment value
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``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
213+
``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
214+
``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
215+
adjustment on parent dpll device
216+
``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting
217+
configuration on given parent dpll
218+
device
219+
``DPLL_A_PIN_PARENT_ID`` parent dpll device id
220+
``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
221+
between a pin and parent dpll device
222+
================================ ==========================================
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222224
All phase related values are provided in pico seconds, which represents
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time difference between signals phase. The negative value means that
@@ -384,6 +386,8 @@ according to attribute purpose.
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frequencies
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``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency
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``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency
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``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attr granularity of phase
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adjustment value
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``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase
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adjustment
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``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase

Documentation/hwmon/aht10.rst

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@@ -20,6 +20,14 @@ Supported chips:
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English: http://www.aosong.com/userfiles/files/media/Data%20Sheet%20AHT20.pdf
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* Aosong DHT20
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25+
Prefix: 'dht20'
26+
27+
Addresses scanned: None
28+
29+
Datasheet: https://www.digikey.co.nz/en/htmldatasheets/production/9184855/0/0/1/101020932
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Author: Johannes Cornelis Draaijer <jcdra1@gmail.com>
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@@ -33,7 +41,7 @@ The address of this i2c device may only be 0x38
3341
Special Features
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----------------
3543

36-
AHT20 has additional CRC8 support which is sent as the last byte of the sensor
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AHT20, DHT20 has additional CRC8 support which is sent as the last byte of the sensor
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values.
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Usage Notes

Documentation/hwmon/nct6683.rst

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@@ -65,6 +65,7 @@ AMD BC-250 NCT6686D EC firmware version 1.0 build 07/28/21
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ASRock X570 NCT6683D EC firmware version 1.0 build 06/28/19
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ASRock X670E NCT6686D EC firmware version 1.0 build 05/19/22
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ASRock B650 Steel Legend WiFi NCT6686D EC firmware version 1.0 build 11/09/23
68+
ASRock Z590 Taichi NCT6686D EC firmware version 1.0 build 01/25/21
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MSI B550 NCT6687D EC firmware version 1.0 build 05/07/20
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MSI X670-P NCT6687D EC firmware version 0.0 build 09/27/22
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MSI X870E NCT6687D EC firmware version 0.0 build 11/13/24

Documentation/netlink/specs/dpll.yaml

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@@ -440,6 +440,12 @@ attribute-sets:
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doc: |
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Capable pin provides list of pins that can be bound to create a
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reference-sync pin pair.
443+
-
444+
name: phase-adjust-gran
445+
type: u32
446+
doc: |
447+
Granularity of phase adjustment, in picoseconds. The value of
448+
phase adjustment must be a multiple of this granularity.
443449
444450
-
445451
name: pin-parent-device
@@ -616,6 +622,7 @@ operations:
616622
- capabilities
617623
- parent-device
618624
- parent-pin
625+
- phase-adjust-gran
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- phase-adjust-min
620627
- phase-adjust-max
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- phase-adjust

Documentation/networking/ip-sysctl.rst

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@@ -3195,12 +3195,13 @@ enhanced_dad - BOOLEAN
31953195
===========
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31973197
ratelimit - INTEGER
3198-
Limit the maximal rates for sending ICMPv6 messages.
3198+
Limit the maximal rates for sending ICMPv6 messages to a particular
3199+
peer.
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32003201
0 to disable any limiting,
3201-
otherwise the minimal space between responses in milliseconds.
3202+
otherwise the space between responses in milliseconds.
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3203-
Default: 1000
3204+
Default: 100
32043205

32053206
ratemask - list of comma separated ranges
32063207
For ICMPv6 message types matching the ranges in the ratemask, limit

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