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sgaud-quicsgaud-quic
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Merge remote-tracking branch tech/all/dt/qcs8300 into qcom-next
2 parents 728bdda + 6ebe22b commit 2c0da2f

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2 files changed

+247
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‎arch/arm64/boot/dts/qcom/qcs8300-ride.dts‎

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,18 @@
3232
enable-active-high;
3333
regulator-always-on;
3434
};
35+
36+
dp0-connector {
37+
compatible = "dp-connector";
38+
label = "DP0";
39+
type = "full-size";
40+
41+
port {
42+
dp0_connector_in: endpoint {
43+
remote-endpoint = <&mdss_dp0_out>;
44+
};
45+
};
46+
};
3547
};
3648

3749
&apps_rsc {
@@ -304,6 +316,30 @@
304316
};
305317
};
306318

319+
&mdss {
320+
status = "okay";
321+
};
322+
323+
&mdss_dp0 {
324+
pinctrl-0 = <&dp_hot_plug_det>;
325+
pinctrl-names = "default";
326+
327+
status = "okay";
328+
};
329+
330+
&mdss_dp0_out {
331+
data-lanes = <0 1 2 3>;
332+
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
333+
remote-endpoint = <&dp0_connector_in>;
334+
};
335+
336+
&mdss_dp0_phy {
337+
vdda-phy-supply = <&vreg_l5a>;
338+
vdda-pll-supply = <&vreg_l4a>;
339+
340+
status = "okay";
341+
};
342+
307343
&qupv3_id_0 {
308344
status = "okay";
309345
};
@@ -346,6 +382,14 @@
346382
};
347383
};
348384

385+
&tlmm {
386+
dp_hot_plug_det: dp-hot-plug-det-state {
387+
pins = "gpio94";
388+
function = "edp0_hot";
389+
bias-disable;
390+
};
391+
};
392+
349393
&uart7 {
350394
status = "okay";
351395
};

‎arch/arm64/boot/dts/qcom/qcs8300.dtsi‎

Lines changed: 203 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4237,14 +4237,216 @@
42374237
#power-domain-cells = <1>;
42384238
};
42394239

4240+
mdss: display-subsystem@ae00000 {
4241+
compatible = "qcom,qcs8300-mdss";
4242+
reg = <0x0 0x0ae00000 0x0 0x1000>;
4243+
reg-names = "mdss";
4244+
4245+
interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
4246+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
4247+
<&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY
4248+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
4249+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
4250+
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
4251+
interconnect-names = "mdp0-mem",
4252+
"mdp1-mem",
4253+
"cpu-cfg";
4254+
4255+
resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>;
4256+
4257+
power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>;
4258+
4259+
clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
4260+
<&gcc GCC_DISP_HF_AXI_CLK>,
4261+
<&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>;
4262+
4263+
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
4264+
interrupt-controller;
4265+
#interrupt-cells = <1>;
4266+
4267+
iommus = <&apps_smmu 0x1000 0x402>;
4268+
4269+
#address-cells = <2>;
4270+
#size-cells = <2>;
4271+
ranges;
4272+
4273+
status = "disabled";
4274+
4275+
mdss_mdp: display-controller@ae01000 {
4276+
compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu";
4277+
reg = <0x0 0x0ae01000 0x0 0x8f000>,
4278+
<0x0 0x0aeb0000 0x0 0x2008>;
4279+
reg-names = "mdp", "vbif";
4280+
4281+
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4282+
<&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
4283+
<&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
4284+
<&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>,
4285+
<&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>;
4286+
clock-names = "bus",
4287+
"iface",
4288+
"lut",
4289+
"core",
4290+
"vsync";
4291+
4292+
assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>;
4293+
assigned-clock-rates = <19200000>;
4294+
4295+
operating-points-v2 = <&mdp_opp_table>;
4296+
power-domains = <&rpmhpd RPMHPD_MMCX>;
4297+
4298+
interrupt-parent = <&mdss>;
4299+
interrupts = <0>;
4300+
4301+
ports {
4302+
#address-cells = <1>;
4303+
#size-cells = <0>;
4304+
4305+
port@0 {
4306+
reg = <0>;
4307+
4308+
dpu_intf0_out: endpoint {
4309+
remote-endpoint = <&mdss_dp0_in>;
4310+
};
4311+
};
4312+
};
4313+
4314+
mdp_opp_table: opp-table {
4315+
compatible = "operating-points-v2";
4316+
4317+
opp-375000000 {
4318+
opp-hz = /bits/ 64 <375000000>;
4319+
required-opps = <&rpmhpd_opp_svs_l1>;
4320+
};
4321+
4322+
opp-500000000 {
4323+
opp-hz = /bits/ 64 <500000000>;
4324+
required-opps = <&rpmhpd_opp_nom>;
4325+
};
4326+
4327+
opp-575000000 {
4328+
opp-hz = /bits/ 64 <575000000>;
4329+
required-opps = <&rpmhpd_opp_turbo>;
4330+
};
4331+
4332+
opp-650000000 {
4333+
opp-hz = /bits/ 64 <650000000>;
4334+
required-opps = <&rpmhpd_opp_turbo_l1>;
4335+
};
4336+
};
4337+
};
4338+
4339+
mdss_dp0_phy: phy@aec2a00 {
4340+
compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
4341+
4342+
reg = <0x0 0x0aec2a00 0x0 0x19c>,
4343+
<0x0 0x0aec2200 0x0 0xec>,
4344+
<0x0 0x0aec2600 0x0 0xec>,
4345+
<0x0 0x0aec2000 0x0 0x1c8>;
4346+
4347+
clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
4348+
<&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
4349+
clock-names = "aux",
4350+
"cfg_ahb";
4351+
4352+
power-domains = <&rpmhpd RPMHPD_MMCX>;
4353+
4354+
#clock-cells = <1>;
4355+
#phy-cells = <0>;
4356+
4357+
status = "disabled";
4358+
};
4359+
4360+
mdss_dp0: displayport-controller@af54000 {
4361+
compatible = "qcom,qcs8300-dp", "qcom,sm8650-dp";
4362+
4363+
reg = <0x0 0x0af54000 0x0 0x200>,
4364+
<0x0 0x0af54200 0x0 0x200>,
4365+
<0x0 0x0af55000 0x0 0xc00>,
4366+
<0x0 0x0af56000 0x0 0x400>;
4367+
4368+
interrupt-parent = <&mdss>;
4369+
interrupts = <12>;
4370+
4371+
clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
4372+
<&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
4373+
<&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
4374+
<&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4375+
<&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4376+
clock-names = "core_iface",
4377+
"core_aux",
4378+
"ctrl_link",
4379+
"ctrl_link_iface",
4380+
"stream_pixel";
4381+
assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4382+
<&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4383+
assigned-clock-parents = <&mdss_dp0_phy 0>,
4384+
<&mdss_dp0_phy 1>;
4385+
phys = <&mdss_dp0_phy>;
4386+
phy-names = "dp";
4387+
4388+
operating-points-v2 = <&dp_opp_table>;
4389+
power-domains = <&rpmhpd RPMHPD_MMCX>;
4390+
4391+
#sound-dai-cells = <0>;
4392+
4393+
status = "disabled";
4394+
4395+
ports {
4396+
#address-cells = <1>;
4397+
#size-cells = <0>;
4398+
4399+
port@0 {
4400+
reg = <0>;
4401+
4402+
mdss_dp0_in: endpoint {
4403+
remote-endpoint = <&dpu_intf0_out>;
4404+
};
4405+
};
4406+
4407+
port@1 {
4408+
reg = <1>;
4409+
4410+
mdss_dp0_out: endpoint { };
4411+
};
4412+
};
4413+
4414+
dp_opp_table: opp-table {
4415+
compatible = "operating-points-v2";
4416+
4417+
opp-160000000 {
4418+
opp-hz = /bits/ 64 <160000000>;
4419+
required-opps = <&rpmhpd_opp_low_svs>;
4420+
};
4421+
4422+
opp-270000000 {
4423+
opp-hz = /bits/ 64 <270000000>;
4424+
required-opps = <&rpmhpd_opp_svs>;
4425+
};
4426+
4427+
opp-540000000 {
4428+
opp-hz = /bits/ 64 <540000000>;
4429+
required-opps = <&rpmhpd_opp_svs_l1>;
4430+
};
4431+
4432+
opp-810000000 {
4433+
opp-hz = /bits/ 64 <810000000>;
4434+
required-opps = <&rpmhpd_opp_nom>;
4435+
};
4436+
};
4437+
};
4438+
};
4439+
42404440
dispcc: clock-controller@af00000 {
42414441
compatible = "qcom,sa8775p-dispcc0";
42424442
reg = <0x0 0x0af00000 0x0 0x20000>;
42434443
clocks = <&gcc GCC_DISP_AHB_CLK>,
42444444
<&rpmhcc RPMH_CXO_CLK>,
42454445
<&rpmhcc RPMH_CXO_CLK_A>,
42464446
<&sleep_clk>,
4247-
<0>, <0>, <0>, <0>,
4447+
<&mdss_dp0_phy 0>,
4448+
<&mdss_dp0_phy 1>,
4449+
<0>, <0>,
42484450
<0>, <0>, <0>, <0>;
42494451
power-domains = <&rpmhpd RPMHPD_MMCX>;
42504452
#clock-cells = <1>;

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