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Jagadeesh KonaKomal Bajaj
Jagadeesh Kona
authored and
Komal Bajaj
committed
FROMGIT: arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
Add OPP tables required to scale DDR and L3 per freq-domain on SA8775P platform. If a single OPP table is used for both CPU domains, then _allocate_opp_table() won't be invoked for CPU4 but instead CPU4 will be added as device under the CPU0 OPP table. Due to this, dev_pm_opp_of_find_icc_paths() won't be invoked for CPU4 device and hence CPU4 won't be able to independently scale it's interconnects. Both CPU0 and CPU4 devices will scale the same ICC path which can lead to one device overwriting the BW vote placed by other device. Hence CPU0 and CPU4 require separate OPP tables to allow independent scaling of DDR and L3 frequencies for each CPU domain, with the final DDR and L3 frequencies being an aggregate of both. Link: https://lore.kernel.org/r/20250415095343.32125-8-quic_rlaggysh@quicinc.com Co-developed-by: Shivnandan Kumar <quic_kshivnan@quicinc.com> Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
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‎arch/arm64/boot/dts/qcom/sa8775p.dtsi‎

Lines changed: 210 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,11 @@
5252
next-level-cache = <&l2_0>;
5353
capacity-dmips-mhz = <1024>;
5454
dynamic-power-coefficient = <100>;
55+
operating-points-v2 = <&cpu0_opp_table>;
56+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
57+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
58+
<&epss_l3_cl0 MASTER_EPSS_L3_APPS
59+
&epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
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l2_0: l2-cache {
5661
compatible = "cache";
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cache-level = <2>;
@@ -76,6 +81,11 @@
7681
next-level-cache = <&l2_1>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
84+
operating-points-v2 = <&cpu0_opp_table>;
85+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
86+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
87+
<&epss_l3_cl0 MASTER_EPSS_L3_APPS
88+
&epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
7989
l2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
@@ -95,6 +105,11 @@
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next-level-cache = <&l2_2>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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operating-points-v2 = <&cpu0_opp_table>;
109+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
110+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3_cl0 MASTER_EPSS_L3_APPS
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&epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
98113
l2_2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
@@ -114,6 +129,11 @@
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next-level-cache = <&l2_3>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
132+
operating-points-v2 = <&cpu0_opp_table>;
133+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
134+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3_cl0 MASTER_EPSS_L3_APPS
136+
&epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
117137
l2_3: l2-cache {
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compatible = "cache";
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cache-level = <2>;
@@ -133,6 +153,11 @@
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next-level-cache = <&l2_4>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
156+
operating-points-v2 = <&cpu4_opp_table>;
157+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
158+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3_cl1 MASTER_EPSS_L3_APPS
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&epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
136161
l2_4: l2-cache {
137162
compatible = "cache";
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cache-level = <2>;
@@ -158,6 +183,11 @@
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next-level-cache = <&l2_5>;
159184
capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
186+
operating-points-v2 = <&cpu4_opp_table>;
187+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
188+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
189+
<&epss_l3_cl1 MASTER_EPSS_L3_APPS
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&epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
161191
l2_5: l2-cache {
162192
compatible = "cache";
163193
cache-level = <2>;
@@ -177,6 +207,11 @@
177207
next-level-cache = <&l2_6>;
178208
capacity-dmips-mhz = <1024>;
179209
dynamic-power-coefficient = <100>;
210+
operating-points-v2 = <&cpu4_opp_table>;
211+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
212+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
213+
<&epss_l3_cl1 MASTER_EPSS_L3_APPS
214+
&epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
180215
l2_6: l2-cache {
181216
compatible = "cache";
182217
cache-level = <2>;
@@ -196,6 +231,11 @@
196231
next-level-cache = <&l2_7>;
197232
capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
234+
operating-points-v2 = <&cpu4_opp_table>;
235+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
236+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3_cl1 MASTER_EPSS_L3_APPS
238+
&epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
199239
l2_7: l2-cache {
200240
compatible = "cache";
201241
cache-level = <2>;
@@ -285,6 +325,176 @@
285325
};
286326
};
287327

328+
cpu0_opp_table: opp-table-cpu0 {
329+
compatible = "operating-points-v2";
330+
opp-shared;
331+
332+
opp-1267200000 {
333+
opp-hz = /bits/ 64 <1267200000>;
334+
opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
335+
};
336+
337+
opp-1363200000 {
338+
opp-hz = /bits/ 64 <1363200000>;
339+
opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
340+
};
341+
342+
opp-1459200000 {
343+
opp-hz = /bits/ 64 <1459200000>;
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opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
345+
};
346+
347+
opp-1536000000 {
348+
opp-hz = /bits/ 64 <1536000000>;
349+
opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
350+
};
351+
352+
opp-1632000000 {
353+
opp-hz = /bits/ 64 <1632000000>;
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opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
355+
};
356+
357+
opp-1708800000 {
358+
opp-hz = /bits/ 64 <1708800000>;
359+
opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
360+
};
361+
362+
opp-1785600000 {
363+
opp-hz = /bits/ 64 <1785600000>;
364+
opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
365+
};
366+
367+
opp-1862400000 {
368+
opp-hz = /bits/ 64 <1862400000>;
369+
opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
370+
};
371+
372+
opp-1939200000 {
373+
opp-hz = /bits/ 64 <1939200000>;
374+
opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
375+
};
376+
377+
opp-2016000000 {
378+
opp-hz = /bits/ 64 <2016000000>;
379+
opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
380+
};
381+
382+
opp-2112000000 {
383+
opp-hz = /bits/ 64 <2112000000>;
384+
opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
385+
};
386+
387+
opp-2188800000 {
388+
opp-hz = /bits/ 64 <2188800000>;
389+
opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
390+
};
391+
392+
opp-2265600000 {
393+
opp-hz = /bits/ 64 <2265600000>;
394+
opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
395+
};
396+
397+
opp-2361600000 {
398+
opp-hz = /bits/ 64 <2361600000>;
399+
opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
400+
};
401+
402+
opp-2457600000 {
403+
opp-hz = /bits/ 64 <2457600000>;
404+
opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
405+
};
406+
407+
opp-2553600000 {
408+
opp-hz = /bits/ 64 <2553600000>;
409+
opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
410+
};
411+
};
412+
413+
cpu4_opp_table: opp-table-cpu4 {
414+
compatible = "operating-points-v2";
415+
opp-shared;
416+
417+
opp-1267200000 {
418+
opp-hz = /bits/ 64 <1267200000>;
419+
opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
420+
};
421+
422+
opp-1363200000 {
423+
opp-hz = /bits/ 64 <1363200000>;
424+
opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
425+
};
426+
427+
opp-1459200000 {
428+
opp-hz = /bits/ 64 <1459200000>;
429+
opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
430+
};
431+
432+
opp-1536000000 {
433+
opp-hz = /bits/ 64 <1536000000>;
434+
opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
435+
};
436+
437+
opp-1632000000 {
438+
opp-hz = /bits/ 64 <1632000000>;
439+
opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
440+
};
441+
442+
opp-1708800000 {
443+
opp-hz = /bits/ 64 <1708800000>;
444+
opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
445+
};
446+
447+
opp-1785600000 {
448+
opp-hz = /bits/ 64 <1785600000>;
449+
opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
450+
};
451+
452+
opp-1862400000 {
453+
opp-hz = /bits/ 64 <1862400000>;
454+
opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
455+
};
456+
457+
opp-1939200000 {
458+
opp-hz = /bits/ 64 <1939200000>;
459+
opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
460+
};
461+
462+
opp-2016000000 {
463+
opp-hz = /bits/ 64 <2016000000>;
464+
opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
465+
};
466+
467+
opp-2112000000 {
468+
opp-hz = /bits/ 64 <2112000000>;
469+
opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
470+
};
471+
472+
opp-2188800000 {
473+
opp-hz = /bits/ 64 <2188800000>;
474+
opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
475+
};
476+
477+
opp-2265600000 {
478+
opp-hz = /bits/ 64 <2265600000>;
479+
opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
480+
};
481+
482+
opp-2361600000 {
483+
opp-hz = /bits/ 64 <2361600000>;
484+
opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
485+
};
486+
487+
opp-2457600000 {
488+
opp-hz = /bits/ 64 <2457600000>;
489+
opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
490+
};
491+
492+
opp-2553600000 {
493+
opp-hz = /bits/ 64 <2553600000>;
494+
opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
495+
};
496+
};
497+
288498
dummy-sink {
289499
compatible = "arm,coresight-dummy-sink";
290500

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