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Add Shikra Support (#613)
Add Shikra Support
2 parents aea160c + d692915 commit 5827f01

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Lines changed: 13295 additions & 56 deletions

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‎Documentation/devicetree/bindings/arm/qcom.yaml‎

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@@ -924,6 +924,24 @@ properties:
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- xiaomi,polaris
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- const: qcom,sdm845
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- items:
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- enum:
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- qcom,shikra-cqm-evk
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- const: qcom,shikra-cqm-som
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- const: qcom,shikra
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- items:
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- enum:
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- qcom,shikra-cqs-evk
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- const: qcom,shikra-cqs-som
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- const: qcom,shikra
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- items:
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- enum:
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- qcom,shikra-iqs-evk
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- const: qcom,shikra-iqs-som
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- const: qcom,shikra
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- items:
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- enum:
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- oneplus,billie2

‎Documentation/devicetree/bindings/cache/qcom,llcc.yaml‎

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@@ -33,6 +33,7 @@ properties:
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- qcom,sc8180x-llcc
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- qcom,sc8280xp-llcc
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- qcom,sdm845-llcc
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- qcom,shikra-llcc
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- qcom,sm6350-llcc
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- qcom,sm7150-llcc
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- qcom,sm8150-llcc
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contains:
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enum:
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- qcom,sc7280-llcc
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- qcom,shikra-llcc
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then:
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properties:
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reg:

‎Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml‎

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@@ -46,6 +46,7 @@ properties:
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- qcom,rpmcc-qcs404
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- qcom,rpmcc-sdm429
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- qcom,rpmcc-sdm660
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- qcom,rpmcc-shikra
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- qcom,rpmcc-sm6115
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- qcom,rpmcc-sm6125
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- qcom,rpmcc-sm6375
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- qcom,rpmcc-qcs404
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- qcom,rpmcc-sdm429
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- qcom,rpmcc-sdm660
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- qcom,rpmcc-shikra
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- qcom,rpmcc-sm6115
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- qcom,rpmcc-sm6125
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‎Documentation/devicetree/bindings/clock/qcom,shikra-dispcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,shikra-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Display Clock & Reset Controller for Qualcomm Shikra SoC
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maintainers:
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- Imran Shaik <imran.shaik@oss.qualcomm.com>
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description: |
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Display clock control module provides the clocks, resets and power
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domains on Qualcomm Shikra SoC platform.
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See also:
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- include/dt-bindings/clock/qcom,shikra-dispcc.h
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properties:
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compatible:
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enum:
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- qcom,shikra-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Board sleep clock
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- description: GPLL0 DISP DIV clock from GCC
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: Byte clock from DSI PHY1
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- description: Pixel clock from DSI PHY1
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required:
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- compatible
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- clocks
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,shikra-gcc.h>
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clock-controller@5f00000 {
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compatible = "qcom,shikra-dispcc";
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reg = <0x05f00000 0x20000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&sleep_clk>,
53+
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&dsi1_phy 0>,
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<&dsi1_phy 1>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,shikra-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Global Clock & Reset Controller on Qualcomm Shikra SoC
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maintainers:
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- Imran Shaik <imran.shaik@oss.qualcomm.com>
11+
- Taniya Das <taniya.das@oss.qualcomm.com>
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description: |
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Global clock control module provides the clocks, resets and power
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domains on Qualcomm Shikra SoC platform.
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See also: include/dt-bindings/clock/qcom,shikra-gcc.h
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properties:
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compatible:
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const: qcom,shikra-gcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: EMAC0 sgmiiphy mac rclk source
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- description: EMAC0 sgmiiphy mac tclk source
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- description: EMAC1 sgmiiphy mac rclk source
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- description: EMAC1 sgmiiphy mac tclk source
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- description: PCIE Pipe clock source
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- description: USB3 phy wrapper pipe clock source
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power-domains:
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items:
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- description: CX domain
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required:
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- compatible
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- clocks
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- power-domains
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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clock-controller@1400000 {
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compatible = "qcom,shikra-gcc";
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reg = <0x01400000 0x1f0000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&sleep_clk>,
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<&emac0_sgmiiphy_rclk>,
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<&emac0_sgmiiphy_tclk>,
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<&emac1_sgmiiphy_rclk>,
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<&emac1_sgmiiphy_tclk>,
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<&pcie_pipe_clk>,
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<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
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power-domains = <&rpmpd RPMPD_VDDCX>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml‎

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title: Qualcomm Graphics Clock & Reset Controller on SM6115
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maintainers:
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- Imran Shaik <imran.shaik@oss.qualcomm.com>
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- Konrad Dybcio <konradybcio@kernel.org>
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description: |
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Qualcomm graphics clock control module provides clocks, resets and power
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domains on Qualcomm SoCs.
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See also: include/dt-bindings/clock/qcom,sm6115-gpucc.h
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See also:
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include/dt-bindings/clock/qcom,shikra-gpucc.h
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include/dt-bindings/clock/qcom,sm6115-gpucc.h
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properties:
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compatible:
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enum:
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- qcom,shikra-gpucc
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- qcom,sm6115-gpucc
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clocks:

‎Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/cpufreq/qcom,shikra-epss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Shikra SoC EPSS
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maintainers:
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- Imran Shaik <imran.shaik@oss.qualcomm.com>
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- Taniya Das <taniya.das@oss.qualcomm.com>
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description: |
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EPSS is a hardware engine used by some Qualcomm SoCs to manage
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frequency in hardware. It is capable of controlling frequency for
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multiple clusters.
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The Qualcomm Shikra SoC EPSS supports up to 12 frequency lookup table
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(LUT) entries.
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properties:
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compatible:
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enum:
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- qcom,shikra-epss
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reg:
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items:
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- description: Frequency domain 0 register region
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- description: Frequency domain 1 register region
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reg-names:
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items:
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- const: freq-domain0
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- const: freq-domain1
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clocks:
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items:
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- description: XO Clock
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- description: GPLL0 Clock
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clock-names:
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items:
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- const: xo
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- const: alternate
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interrupts:
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items:
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- description: IRQ line for DCVSH 0
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- description: IRQ line for DCVSH 1
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interrupt-names:
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items:
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- const: dcvsh-irq-0
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- const: dcvsh-irq-1
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'#freq-domain-cells':
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const: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
64+
- reg
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- '#freq-domain-cells'
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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cpufreq@fd91000 {
84+
compatible = "qcom,shikra-epss";
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reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>;
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reg-names = "freq-domain0", "freq-domain1";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gpll0>;
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clock-names = "xo", "alternate";
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
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#freq-domain-cells = <1>;
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#clock-cells = <1>;
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};
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};
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...

‎Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml‎

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- qcom,sa8775p-inline-crypto-engine
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- qcom,sc7180-inline-crypto-engine
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- qcom,sc7280-inline-crypto-engine
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- qcom,shikra-inline-crypto-engine
2122
- qcom,sm8450-inline-crypto-engine
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- qcom,sm8550-inline-crypto-engine
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- qcom,sm8650-inline-crypto-engine

‎Documentation/devicetree/bindings/crypto/qcom,prng.yaml‎

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- qcom,sa8255p-trng
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- qcom,sa8775p-trng
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- qcom,sc7280-trng
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- qcom,shikra-trng
2829
- qcom,sm8450-trng
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- qcom,sm8550-trng
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- qcom,sm8650-trng

‎Documentation/devicetree/bindings/crypto/qcom-qce.yaml‎

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- qcom,qcs8300-qce
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- qcom,sa8775p-qce
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- qcom,sc7280-qce
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- qcom,shikra-qce
5253
- qcom,sm6350-qce
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- qcom,sm8250-qce
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- qcom,sm8350-qce

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