arm64: dts: qcom: Add flags to advertise PCIe ASPM incompatibility

Add l0s/l1 incompatibility flags for respecitve ports on the TC9563
PCIe switch.

Signed-off-by: Sushrut Shree Trivedi <sushruts@qti.qualcomm.com>

Author: sushrut-trivedi

arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso

@@ -102,6 +102,9 @@
 		pinctrl-0 = <&pcie0_tc9563_resx_n>;
 		pinctrl-names = "default";
 
+		aspm-no-l0s;
+		aspm-no-l1;
+
 		pcie@1,0 {
 			reg = <0x20800 0x0 0x0 0x0 0x0>;
 			#address-cells = <3>;
@@ -110,6 +113,9 @@
 			device_type = "pci";
 			ranges;
 			bus-range = <0x3 0xff>;
+
+			aspm-no-l0s;
+			aspm-no-l1;
 		};
 
 		pcie@2,0 {
@@ -120,6 +126,9 @@
 			device_type = "pci";
 			ranges;
 			bus-range = <0x4 0xff>;
+
+			aspm-no-l0s;
+			aspm-no-l1;
 		};
 
 		pcie@3,0 {
@@ -197,6 +206,9 @@
 		pinctrl-0 = <&pcie1_tc9563_resx_n>;
 		pinctrl-names = "default";
 
+		aspm-no-l0s;
+		aspm-no-l1;
+
 		pcie@1,0 {
 			reg = <0x40800 0x0 0x0 0x0 0x0>;
 			#address-cells = <3>;
@@ -205,6 +217,9 @@
 			device_type = "pci";
 			ranges;
 			bus-range = <0x3 0xff>;
+
+			aspm-no-l0s;
+			aspm-no-l1;
 		};
 
 		pcie@2,0 {
@@ -215,6 +230,9 @@
 			device_type = "pci";
 			ranges;
 			bus-range = <0x4 0xff>;
+
+			aspm-no-l0s;
+			aspm-no-l1;
 		};
 
 		pcie@3,0 {

arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts

@@ -1021,6 +1021,9 @@
 		pinctrl-0 = <&tc9563_resx_n>;
 		pinctrl-names = "default";
 
+		aspm-no-l0s;
+		aspm-no-l1;
+
 		pcie1_switch0_dsp1: pcie@1,0 {
 			reg = <0x20800 0x0 0x0 0x0 0x0>;
 			#address-cells = <3>;
@@ -1029,6 +1032,9 @@
 			device_type = "pci";
 			ranges;
 			bus-range = <0x3 0xff>;
+
+			aspm-no-l0s;
+			aspm-no-l1;
 		};
 
 		pcie@2,0 {
@@ -1040,6 +1046,9 @@
 			ranges;
 			bus-range = <0x4 0xff>;
 
+			aspm-no-l0s;
+			aspm-no-l1;
+
 			/* Renesas μPD720201 PCIe USB3.0 Host Controller */
 			usb-controller@0,0 {
 				compatible = "pci1912,0014";